[PATCH] D91160: [NFC] Use [MC]Register for Hexagon target
Mircea Trofin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 10 07:41:36 PST 2020
mtrofin added a comment.
Maybe the popular RegisterRef can be moved to Register.h? Would that complicate this patch?
================
Comment at: llvm/lib/Target/Hexagon/BitTracker.h:134
- unsigned Reg;
+ Register Reg;
uint16_t Pos;
----------------
are Reg and Pos const?
================
Comment at: llvm/lib/Target/Hexagon/BitTracker.h:146
+ Register Reg;
+ unsigned Sub;
};
----------------
Are Reg and Sub const? marking them so would help readability, and also ensure we don't accidentally yank the initializer in the ctor.
================
Comment at: llvm/lib/Target/Hexagon/HexagonBlockRanges.h:34
struct RegisterRef {
+ llvm::Register Reg;
----------------
weird... there was one of these earlier. Not sure if hoisting it in a common .h may make sense, but otherwise the comments are the same (const-ing Reg and Sub)
================
Comment at: llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp:86
struct RegisterSubReg {
- unsigned Reg, SubReg;
+ Register Reg;
+ unsigned SubReg;
----------------
seems like a popular design
================
Comment at: llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp:190
- unsigned Reg, Sub;
+ Register Reg, Sub;
};
----------------
4th RegisterRef.
Sub is probably unsigned?
================
Comment at: llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp:51
struct RegisterSubReg {
- unsigned R, S;
+ Register R;
+ unsigned S;
----------------
5th RegisterRef :)
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D91160/new/
https://reviews.llvm.org/D91160
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