[llvm] 642b21b - [AArch64] Enable RAS 1.1 system registers in all AArch64
Pablo Barrio via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 10 04:13:56 PST 2020
Author: Pablo Barrio
Date: 2020-11-10T12:13:33Z
New Revision: 642b21beba4c75fa2142413e7e4b9140d3194d19
URL: https://github.com/llvm/llvm-project/commit/642b21beba4c75fa2142413e7e4b9140d3194d19
DIFF: https://github.com/llvm/llvm-project/commit/642b21beba4c75fa2142413e7e4b9140d3194d19.diff
LOG: [AArch64] Enable RAS 1.1 system registers in all AArch64
Some use cases (e.g. kernel devs) have strict requirements to only enable
features available with -march=armv8-a, e.g. no armv8.1-a. Enabling RAS 1.1 in
all AArch64 means they can consider to support it.
Bear in mind that the first versions of the Armv8 architecture still do not
support RAS 1.1. This patch only lets devs write code with the user-friendly
register mnemonic instead of the ugly generic S<op0>_<op1>_<Cn>_<Cm>_<op2>.
They still need to place runtime checks to make sure that the CPU to run on
supports RAS 1.1.
Differential Revision: https://reviews.llvm.org/D90594
Added:
Modified:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/test/MC/AArch64/armv8.4a-ras.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 591301017f9a..8bf85de4dc51 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -280,11 +280,6 @@ def FeatureNV : SubtargetFeature<
"nv", "HasNV", "true",
"Enable v8.4-A Nested Virtualization Enchancement">;
-def FeatureRASv8_4 : SubtargetFeature<
- "rasv8_4", "HasRASv8_4", "true",
- "Enable v8.4-A Reliability, Availability and Serviceability extension",
- [FeatureRAS]>;
-
def FeatureMPAM : SubtargetFeature<
"mpam", "HasMPAM", "true",
"Enable v8.4-A Memory system Partitioning and Monitoring extension">;
@@ -427,7 +422,7 @@ def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
- FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
+ FeatureNV, FeatureMPAM, FeatureDIT,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
FeatureFMI, FeatureRCPC_IMMO]>;
@@ -454,7 +449,7 @@ def HasV8_0rOps : SubtargetFeature<
FeatureComplxNum, FeatureCCIDX, FeatureJS,
FeaturePA, FeatureRCPC,
//v8.4
- FeatureDotProd, FeatureFP16FML, FeatureRASv8_4, FeatureTRACEV8_4,
+ FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4,
FeatureTLB_RMI, FeatureFMI, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
//v8.5
FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict]>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 52608a6249c8..8798890b2fe4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -46,9 +46,6 @@ def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">,
def HasNV : Predicate<"Subtarget->hasNV()">,
AssemblerPredicate<(all_of FeatureNV), "nv">;
-def HasRASv8_4 : Predicate<"Subtarget->hasRASv8_4()">,
- AssemblerPredicate<(all_of FeatureRASv8_4), "rasv8_4">;
-
def HasMPAM : Predicate<"Subtarget->hasMPAM()">,
AssemblerPredicate<(all_of FeatureMPAM), "mpam">;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 0710781b2fbc..67c682ca433a 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -130,7 +130,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
// ARMv8.4 extensions
bool HasNV = false;
- bool HasRASv8_4 = false;
bool HasMPAM = false;
bool HasDIT = false;
bool HasTRACEV8_4 = false;
@@ -486,7 +485,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool hasComplxNum() const { return HasComplxNum; }
bool hasNV() const { return HasNV; }
- bool hasRASv8_4() const { return HasRASv8_4; }
bool hasMPAM() const { return HasMPAM; }
bool hasDIT() const { return HasDIT; }
bool hasTRACEV8_4() const { return HasTRACEV8_4; }
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 76117012731b..699fd36be251 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1335,13 +1335,11 @@ def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
// v8.4a RAS registers
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureRASv8_4} }] in {
def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>;
def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>;
def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;
-} // FeatureRASv8_4
// v8.4a MPAM registers
// Op0 Op1 CRn CRm Op2
diff --git a/llvm/test/MC/AArch64/armv8.4a-ras.s b/llvm/test/MC/AArch64/armv8.4a-ras.s
index 5e96d2711a0b..4bf833710a49 100644
--- a/llvm/test/MC/AArch64/armv8.4a-ras.s
+++ b/llvm/test/MC/AArch64/armv8.4a-ras.s
@@ -1,8 +1,6 @@
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK
// RUN: FileCheck --check-prefix=CHECK-RO < %t %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
-
//------------------------------------------------------------------------------
// ARMV8.4-A RAS Extensions
//------------------------------------------------------------------------------
@@ -14,32 +12,24 @@
//CHECK: msr ERXPFGCTL_EL1, x0 // encoding: [0xa0,0x54,0x18,0xd5]
//CHECK: mrs x0, ERXPFGCTL_EL1 // encoding: [0xa0,0x54,0x38,0xd5]
-//CHECK-ERROR: error: expected writable system register or pstate
-//CHECK-ERROR: error: expected readable system register
msr ERXPFGCDN_EL1, x0
mrs x0,ERXPFGCDN_EL1
//CHECK: msr ERXPFGCDN_EL1, x0 // encoding: [0xc0,0x54,0x18,0xd5]
//CHECK: mrs x0, ERXPFGCDN_EL1 // encoding: [0xc0,0x54,0x38,0xd5]
-//CHECK-ERROR: error: expected writable system register or pstate
-//CHECK-ERROR: error: expected readable system register
msr ERXMISC2_EL1, x0
mrs x0, ERXMISC2_EL1
//CHECK: msr ERXMISC2_EL1, x0 // encoding: [0x40,0x55,0x18,0xd5]
//CHECK: mrs x0, ERXMISC2_EL1 // encoding: [0x40,0x55,0x38,0xd5]
-//CHECK-ERROR: error: expected writable system register or pstate
-//CHECK-ERROR: error: expected readable system register
msr ERXMISC3_EL1, x0
mrs x0, ERXMISC3_EL1
//CHECK: msr ERXMISC3_EL1, x0 // encoding: [0x60,0x55,0x18,0xd5]
//CHECK: mrs x0, ERXMISC3_EL1 // encoding: [0x60,0x55,0x38,0xd5]
-//CHECK-ERROR: error: expected writable system register or pstate
-//CHECK-ERROR: error: expected readable system register
// Read-only registers:
@@ -48,5 +38,3 @@
//CHECK: mrs x0, ERXPFGF_EL1 // encoding: [0x80,0x54,0x38,0xd5]
//CHECK-RO: error: expected writable system register or pstate
-//CHECK-ERROR: error: expected readable system register
-//CHECK-ERROR: error: expected writable system register or pstate
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