[PATCH] D91097: [IR] [TableGen] Cleanup pass over the IR TableGen files, part 2

[Paul C. Anagnostopoulos via Phabricator via llvm-commits]

Paul-C-Anagnostopoulos created this revision.
Paul-C-Anagnostopoulos added reviewers: lattner, nhaehnle, jholewinski.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
Paul-C-Anagnostopoulos requested review of this revision.

This is the final patch for the IR TableGen files cleanup.

It deals with the intrinsics for NVVM.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91097

Files:
  llvm/include/llvm/IR/IntrinsicsNVVM.td


Index: llvm/include/llvm/IR/IntrinsicsNVVM.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsNVVM.td
+++ llvm/include/llvm/IR/IntrinsicsNVVM.td
@@ -128,7 +128,7 @@
      !eq(A.ptx_elt_type, "u4") : [A],
      !eq(A.ptx_elt_type, "b1") : [A],
      // the rest are FP ops identified by accumulator & result type.
-     1: [D, C]
+     true: [D, C]
      );
    string ret = !foldl("", id_frags, a, b, !strconcat(a, ".", b.ptx_elt_type));
 }
@@ -162,14 +162,16 @@
             list<string> TypeC, list<string> TypeD> {
   list<list<WMMA_REGS>> ret =
      !foldl([]<list<WMMA_REGS>>, Geom, t1, geom, !listconcat(t1,
-     !foldl([]<list<WMMA_REGS>>, TypeA, t2, type_a, !listconcat(t2,
-     !foldl([]<list<WMMA_REGS>>, !if(!size(TypeB), TypeB, [type_a]), t3, type_b, !listconcat(t3,
-     !foldl([]<list<WMMA_REGS>>, TypeC, t4, type_c, !listconcat(t4,
-     !foldl([]<list<WMMA_REGS>>, !if(!size(TypeD), TypeD, [type_c]), t5, type_d, !listconcat(t5,
-            [[WMMA_REGS<geom, "a", type_a>,
-              WMMA_REGS<geom, "b", type_b>,
-              WMMA_REGS<geom, "c", type_c>,
-              WMMA_REGS<geom, "d", type_d>]]))))))))));
+       !foldl([]<list<WMMA_REGS>>, TypeA, t2, type_a, !listconcat(t2,
+         !foldl([]<list<WMMA_REGS>>, !if(!size(TypeB), TypeB, [type_a]), t3,
+                type_b, !listconcat(t3,
+           !foldl([]<list<WMMA_REGS>>, TypeC, t4, type_c, !listconcat(t4,
+             !foreach(type_d, !if(!size(TypeD), TypeD, [type_c]),
+                      [WMMA_REGS<geom, "a", type_a>,
+                       WMMA_REGS<geom, "b", type_b>,
+                       WMMA_REGS<geom, "c", type_c>,
+                       WMMA_REGS<geom, "d", type_d>])))))))));
+
    // Debugging aid for readable representation of the list above.
    list<list<string>> ops = !foreach(x, ret, [x[0].gft, x[1].gft, x[2].gft, x[3].gft]);
 }
@@ -177,9 +179,8 @@
 class MMA_LDST_OPS<list<string> Geom, list<string> Frags, list<string> Types> {
   list<WMMA_REGS> ret =
      !foldl([]<WMMA_REGS>, Geom, t1, geom, !listconcat(t1,
-     !foldl([]<WMMA_REGS>, Frags, t2, frag, !listconcat(t2,
-     !foldl([]<WMMA_REGS>, Types, t3, type, !listconcat(t3,
-            [WMMA_REGS<geom, frag, type>]))))));
+       !foldl([]<WMMA_REGS>, Frags, t2, frag, !listconcat(t2,
+         !foreach(type, Types, WMMA_REGS<geom, frag, type>)))));
    // Debugging aid for readable representation of the list above.
    list<string> ops = !foreach(x, ret, x.gft);
 }
@@ -294,7 +295,7 @@
     !eq(t, "s4") : [],
     !eq(t, "u4") : [],
     // All other (non sub-int) are OK.
-    1: [1]
+    true: [1]
   );
 }
 
@@ -307,8 +308,8 @@
   string Name = "int_nvvm_shfl_" # Suffix;
   string Builtin = "__nvvm_shfl_" # Suffix;
   string IntrName = "llvm.nvvm.shfl." # !subst("_",".", Suffix);
-  list<int> withGccBuiltin = !if(return_pred, [], [1]);
-  list<int> withoutGccBuiltin = !if(return_pred, [1], []);
+  bit withGccBuiltin = !not(return_pred);
+  bit withoutGccBuiltin = return_pred;
   LLVMType OpType = !cond(
     !eq(type,"i32"): llvm_i32_ty,
     !eq(type,"f32"): llvm_float_ty);
@@ -3998,18 +3999,18 @@
 // SHUFFLE
 //
 // Generate intrinsics for all variants of shfl instruction.
-foreach sync = [0, 1] in {
+foreach sync = [false, true] in {
   foreach mode = ["up", "down", "bfly", "idx"] in {
     foreach type = ["i32", "f32"] in {
-      foreach return_pred = [0, 1] in {
+      foreach return_pred = [false, true] in {
         foreach i = [SHFL_INFO<sync, mode, type, return_pred>] in {
-          foreach _ = i.withGccBuiltin in {
+          if i.withGccBuiltin then {
             def i.Name : GCCBuiltin<i.Builtin>,
                          Intrinsic<i.RetTy, i.ArgsTy,
                                    [IntrInaccessibleMemOnly, IntrConvergent],
                                    i.IntrName>;
           }
-          foreach _ = i.withoutGccBuiltin in {
+          if i.withoutGccBuiltin then {
             def i.Name : Intrinsic<i.RetTy, i.ArgsTy,
                          [IntrInaccessibleMemOnly, IntrConvergent], i.IntrName>;
           }


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