[llvm] 4265cba - [RISCV] Make SIGN_EXTEND_INREG from i8/i16 legal when Zbb extension is enabled.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-11-09T10:13:45-08:00
New Revision: 4265cbaa34815f0a6d81f3479f59903f3f2f7bee

URL: https://github.com/llvm/llvm-project/commit/4265cbaa34815f0a6d81f3479f59903f3f2f7bee
DIFF: https://github.com/llvm/llvm-project/commit/4265cbaa34815f0a6d81f3479f59903f3f2f7bee.diff

LOG: [RISCV] Make SIGN_EXTEND_INREG from i8/i16 legal when Zbb extension is enabled.

This produces better code for sign extend to i64 on RV32 target.

Differential Revision: https://reviews.llvm.org/D91023

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    llvm/test/CodeGen/RISCV/rv32Zbb.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b24d19cc6c51..76fd93830aa5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -111,8 +111,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 
-  for (auto VT : {MVT::i1, MVT::i8, MVT::i16})
-    setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+  if (!Subtarget.hasStdExtZbb()) {
+    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
+    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
+  }
 
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::ADD, MVT::i32, Custom);

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 2a633feeb00f..009d8cbca76e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -825,15 +825,10 @@ def : Pat<(cttz GPR:$rs1), (CTZ GPR:$rs1)>;
 def : Pat<(ctpop GPR:$rs1), (PCNT GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb]
 
-let Predicates = [HasStdExtZbb, IsRV32] in
-def : Pat<(sra (shl GPR:$rs1, (i32 24)), (i32 24)), (SEXTB GPR:$rs1)>;
-let Predicates = [HasStdExtZbb, IsRV64] in
-def : Pat<(sra (shl GPR:$rs1, (i64 56)), (i64 56)), (SEXTB GPR:$rs1)>;
-
-let Predicates = [HasStdExtZbb, IsRV32] in
-def : Pat<(sra (shl GPR:$rs1, (i32 16)), (i32 16)), (SEXTH GPR:$rs1)>;
-let Predicates = [HasStdExtZbb, IsRV64] in
-def : Pat<(sra (shl GPR:$rs1, (i64 48)), (i64 48)), (SEXTH GPR:$rs1)>;
+let Predicates = [HasStdExtZbb] in {
+def : Pat<(sext_inreg GPR:$rs1, i8), (SEXTB GPR:$rs1)>;
+def : Pat<(sext_inreg GPR:$rs1, i16), (SEXTH GPR:$rs1)>;
+}
 
 let Predicates = [HasStdExtZbb] in {
 def : Pat<(smin GPR:$rs1, GPR:$rs2), (MIN  GPR:$rs1, GPR:$rs2)>;

diff  --git a/llvm/test/CodeGen/RISCV/rv32Zbb.ll b/llvm/test/CodeGen/RISCV/rv32Zbb.ll
index c0776265601a..c6c771c18497 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbb.ll
@@ -824,18 +824,14 @@ define i64 @sextb_i64(i64 %a) nounwind {
 ;
 ; RV32IB-LABEL: sextb_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sext.b a2, a0
-; RV32IB-NEXT:    slli a0, a0, 24
+; RV32IB-NEXT:    sext.b a0, a0
 ; RV32IB-NEXT:    srai a1, a0, 31
-; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: sextb_i64:
 ; RV32IBB:       # %bb.0:
-; RV32IBB-NEXT:    sext.b a2, a0
-; RV32IBB-NEXT:    slli a0, a0, 24
+; RV32IBB-NEXT:    sext.b a0, a0
 ; RV32IBB-NEXT:    srai a1, a0, 31
-; RV32IBB-NEXT:    mv a0, a2
 ; RV32IBB-NEXT:    ret
   %shl = shl i64 %a, 56
   %shr = ashr exact i64 %shl, 56
@@ -873,18 +869,14 @@ define i64 @sexth_i64(i64 %a) nounwind {
 ;
 ; RV32IB-LABEL: sexth_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sext.h a2, a0
-; RV32IB-NEXT:    slli a0, a0, 16
+; RV32IB-NEXT:    sext.h a0, a0
 ; RV32IB-NEXT:    srai a1, a0, 31
-; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: sexth_i64:
 ; RV32IBB:       # %bb.0:
-; RV32IBB-NEXT:    sext.h a2, a0
-; RV32IBB-NEXT:    slli a0, a0, 16
+; RV32IBB-NEXT:    sext.h a0, a0
 ; RV32IBB-NEXT:    srai a1, a0, 31
-; RV32IBB-NEXT:    mv a0, a2
 ; RV32IBB-NEXT:    ret
   %shl = shl i64 %a, 48
   %shr = ashr exact i64 %shl, 48