[PATCH] D91016: [RISCV] Add isel patterns to match sbset/sbclr/sbinv/sbext even if the shift amount isn't masked.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 9 09:56:22 PST 2020


This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc0dd22e44a66: [RISCV] Add isel patterns to match sbset/sbclr/sbinv/sbext even if the shift… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91016/new/

https://reviews.llvm.org/D91016

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32Zbs.ll
  llvm/test/CodeGen/RISCV/rv64Zbs.ll

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