[PATCH] D90842: [VE] fastcc with vector register passing

[Simon Moll via Phabricator via llvm-commits]

simoll added a comment.

Here is why the patches are structured this way relying on `fastcc`:
My actual goal is to put a patch on phabricator that demonstrates the hpce/develop isel mechanism for vector instructions. This should come with single vector instruction tests (one vector inst emitted per test function).

Using `fastcc` we can write single vector instruction tests that do not require any vld nor vst nor vor, if we order the vector operands in IR to match the vreg order of the CC.
However, to emit any valid vector instruction code in the first place, i need LVLGen upstream (D90850 <https://reviews.llvm.org/D90850>) and to upstream LVLGen we need a test for it. The `VOR` required for `fastcc` is such a test and it does not require any isel patterns.

This current patch (D90842 <https://reviews.llvm.org/D90842>) is just a stub for `fastcc` to make D90850 <https://reviews.llvm.org/D90850> smaller.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90842/new/

https://reviews.llvm.org/D90842