[llvm] 19313ed - [RISCV] Remove assertsexti32 from a couple B extension isel patterns that don't demanded the sign extended bits.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-11-07T22:43:16-08:00
New Revision: 19313ed580af4d851c12c4b7c244795df9967e2f

URL: https://github.com/llvm/llvm-project/commit/19313ed580af4d851c12c4b7c244795df9967e2f
DIFF: https://github.com/llvm/llvm-project/commit/19313ed580af4d851c12c4b7c244795df9967e2f.diff

LOG: [RISCV] Remove assertsexti32 from a couple B extension isel patterns that don't demanded the sign extended bits.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 0b6d76eed72f..cc488f638133 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -1061,12 +1061,12 @@ def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (PCNTW GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
-def : Pat<(sext_inreg (or (shl (assertsexti32 GPR:$rs2), (i64 16)),
-                          (and (assertsexti32 GPR:$rs1), 0x000000000000FFFF)),
+def : Pat<(sext_inreg (or (shl GPR:$rs2, (i64 16)),
+                          (and GPR:$rs1, 0x000000000000FFFF)),
                       i32),
           (PACKW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
-              (srl (and (assertsexti32 GPR:$rs1), 0x00000000FFFF0000),
+              (srl (and GPR:$rs1, 0x00000000FFFF0000),
                    (i64 16))),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]