[PATCH] D91023: [RISCV] Make SIGN_EXTEND_INREG from i8/i16 legal when Zbb extension is enabled.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 7 19:14:44 PST 2020
craig.topper created this revision.
craig.topper added reviewers: asb, lenary, luismarques, frasercrmck, lewis-revill, PaoloS.
Herald added subscribers: NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.
craig.topper requested review of this revision.
Herald added a subscriber: MaskRay.
This produces better code for sign extend to i64 on RV32 target.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D91023
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbb.ll
Index: llvm/test/CodeGen/RISCV/rv32Zbb.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv32Zbb.ll
+++ llvm/test/CodeGen/RISCV/rv32Zbb.ll
@@ -824,18 +824,14 @@
;
; RV32IB-LABEL: sextb_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: sext.b a2, a0
-; RV32IB-NEXT: slli a0, a0, 24
+; RV32IB-NEXT: sext.b a0, a0
; RV32IB-NEXT: srai a1, a0, 31
-; RV32IB-NEXT: mv a0, a2
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: sextb_i64:
; RV32IBB: # %bb.0:
-; RV32IBB-NEXT: sext.b a2, a0
-; RV32IBB-NEXT: slli a0, a0, 24
+; RV32IBB-NEXT: sext.b a0, a0
; RV32IBB-NEXT: srai a1, a0, 31
-; RV32IBB-NEXT: mv a0, a2
; RV32IBB-NEXT: ret
%shl = shl i64 %a, 56
%shr = ashr exact i64 %shl, 56
@@ -873,18 +869,14 @@
;
; RV32IB-LABEL: sexth_i64:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: sext.h a2, a0
-; RV32IB-NEXT: slli a0, a0, 16
+; RV32IB-NEXT: sext.h a0, a0
; RV32IB-NEXT: srai a1, a0, 31
-; RV32IB-NEXT: mv a0, a2
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: sexth_i64:
; RV32IBB: # %bb.0:
-; RV32IBB-NEXT: sext.h a2, a0
-; RV32IBB-NEXT: slli a0, a0, 16
+; RV32IBB-NEXT: sext.h a0, a0
; RV32IBB-NEXT: srai a1, a0, 31
-; RV32IBB-NEXT: mv a0, a2
; RV32IBB-NEXT: ret
%shl = shl i64 %a, 48
%shr = ashr exact i64 %shl, 48
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -845,15 +845,10 @@
def : Pat<(ctpop GPR:$rs1), (PCNT GPR:$rs1)>;
} // Predicates = [HasStdExtZbb]
-let Predicates = [HasStdExtZbb, IsRV32] in
-def : Pat<(sra (shl GPR:$rs1, (i32 24)), (i32 24)), (SEXTB GPR:$rs1)>;
-let Predicates = [HasStdExtZbb, IsRV64] in
-def : Pat<(sra (shl GPR:$rs1, (i64 56)), (i64 56)), (SEXTB GPR:$rs1)>;
-
-let Predicates = [HasStdExtZbb, IsRV32] in
-def : Pat<(sra (shl GPR:$rs1, (i32 16)), (i32 16)), (SEXTH GPR:$rs1)>;
-let Predicates = [HasStdExtZbb, IsRV64] in
-def : Pat<(sra (shl GPR:$rs1, (i64 48)), (i64 48)), (SEXTH GPR:$rs1)>;
+let Predicates = [HasStdExtZbb] in {
+def : Pat<(sext_inreg GPR:$rs1, i8), (SEXTB GPR:$rs1)>;
+def : Pat<(sext_inreg GPR:$rs1, i16), (SEXTH GPR:$rs1)>;
+}
let Predicates = [HasStdExtZbb] in {
def : Pat<(smin GPR:$rs1, GPR:$rs2), (MIN GPR:$rs1, GPR:$rs2)>;
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -111,8 +111,11 @@
setOperationAction(ISD::VACOPY, MVT::Other, Expand);
setOperationAction(ISD::VAEND, MVT::Other, Expand);
- for (auto VT : {MVT::i1, MVT::i8, MVT::i16})
- setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+ if (!Subtarget.hasStdExtZbb()) {
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
+ }
if (Subtarget.is64Bit()) {
setOperationAction(ISD::ADD, MVT::i32, Custom);
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