[llvm] b874575 - [VE][NFC] Update rem.ll regression test

[Kazushi Marukawa via llvm-commits]

Author: Kazushi (Jam) Marukawa
Date: 2020-11-06T10:44:29+09:00
New Revision: b8745751f167f16717d36867ca46328afa4b7919

URL: https://github.com/llvm/llvm-project/commit/b8745751f167f16717d36867ca46328afa4b7919
DIFF: https://github.com/llvm/llvm-project/commit/b8745751f167f16717d36867ca46328afa4b7919.diff

LOG: [VE][NFC] Update rem.ll regression test

`Replace ISD::SREM handling with KnownBits::srem to reduce code
duplication` (bf04e34383b06f1b71819de7f34a1a1de2cdb6a4) changed
the result of rem.ll regression test.  So, updating it.

Added: 
    

Modified: 
    llvm/test/CodeGen/VE/Scalar/rem.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/VE/Scalar/rem.ll b/llvm/test/CodeGen/VE/Scalar/rem.ll
index d4e72ca86696..2fb6f1845eb8 100644
--- a/llvm/test/CodeGen/VE/Scalar/rem.ll
+++ b/llvm/test/CodeGen/VE/Scalar/rem.ll
@@ -252,7 +252,7 @@ define signext i32 @remi32li(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    divs.w.sx %s0, 3, %s1
 ; CHECK-NEXT:    muls.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, 3, %s0
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i32 3, %b
   ret i32 %r