[PATCH] D90738: [RISCV] Support Zfh half-precision floating-point extension.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td:273
+// Moves (no conversion)
+def : Pat<(bitconvert GPR:$rs1), (FMV_H_X GPR:$rs1)>;
+def : Pat<(bitconvert FPR16:$rs1), (FMV_X_H FPR16:$rs1)>;
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I don't think these bitconvert patterns make sense. bitconvert must have the same number of bits on both sides. The GPR will be i32 or i64 which will never have the same number of bit as f16.


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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90738/new/

https://reviews.llvm.org/D90738