[PATCH] D90635: [TableGen] Add true and false literals to represent booleans
Paul C. Anagnostopoulos via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 5 13:13:01 PST 2020
Paul-C-Anagnostopoulos added a comment.
Yes, I think it would be quite disruptive. But a strong stylistic suggestion in the documentation is in order.
Note that I have already modified one TableGen file to this:
bits<3> foo = {true, false, true};
Because the bits field is actually treated as three booleans. Consider status registers and predicate registers, too.
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https://reviews.llvm.org/D90635/new/
https://reviews.llvm.org/D90635
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