[llvm] ce1270f - [RISCV] Remove shadow register list passed to AllocateReg when allocating FP registers for calling convention
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 5 09:50:29 PST 2020
Author: Craig Topper
Date: 2020-11-05T09:49:42-08:00
New Revision: ce1270fc7e3d71f5769d4f9d151b275c6733c89d
URL: https://github.com/llvm/llvm-project/commit/ce1270fc7e3d71f5769d4f9d151b275c6733c89d
DIFF: https://github.com/llvm/llvm-project/commit/ce1270fc7e3d71f5769d4f9d151b275c6733c89d.diff
LOG: [RISCV] Remove shadow register list passed to AllocateReg when allocating FP registers for calling convention
The _F and _D registers are already sub/super registers. When one gets allocated all its aliases are already marked as allocated. We don't need to explicitly shadow it too.
I believe shadow is for calling conventions like 64-bit Windows on X86 where have rules like this
CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
[XMM0, XMM1, XMM2, XMM3]>>
For that calling convention the argument number determines which register is used regardless of how many scalars or vectors came before it.
Removing this removes a question I had in D90738.
Differential Revision: https://reviews.llvm.org/D90801
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 17b3a168b9cb..72ecf55e672b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1669,9 +1669,9 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
// Allocate to a register if possible, or else a stack slot.
Register Reg;
if (ValVT == MVT::f32 && !UseGPRForF32)
- Reg = State.AllocateReg(ArgFPR32s, ArgFPR64s);
+ Reg = State.AllocateReg(ArgFPR32s);
else if (ValVT == MVT::f64 && !UseGPRForF64)
- Reg = State.AllocateReg(ArgFPR64s, ArgFPR32s);
+ Reg = State.AllocateReg(ArgFPR64s);
else
Reg = State.AllocateReg(ArgGPRs);
unsigned StackOffset =
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