[PATCH] D90738: [RISCV] Support Zfh half-precision floating-point extension.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1705
   if (ValVT == MVT::f32 && !UseGPRForF32)
     Reg = State.AllocateReg(ArgFPR32s, ArgFPR64s);
   else if (ValVT == MVT::f64 && !UseGPRForF64)
----------------
craig.topper wrote:
> The second argument is shadow regs. Do we need a way to shaddow ArgFPR16s here.
Thinking more about this, since the fp registers are sub/super registers, we may not need shadows registers here at all.

I've posted D90801 to remove the shadow arguments here.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1875
       break;
+    } else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f16) {
+      Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTH_RV64, DL, MVT::i64, Val);
----------------
Drop the else. The break in the previous if already exited.

The other option would be to remove breaks and pull the BITCAST below into a final else.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td:292
+def : PatFpr16Fpr16<fcopysign, FSGNJ_H>;
+def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>;
+
----------------
I think its possible to have an fcopysign with a FPR32 or FPR64 second argument. It's also possible to have a fcopysign with a FPR32 or FPR64 first argument and an FPR16 second argument.

RISCVInstrInfoD.td has these patterns because of that

```
def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>;                                                                                                                                                                                                    
def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,                                                                                                                                                                                                       
                                                              0b111))>; 
```


Repository:
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  https://reviews.llvm.org/D90738/new/

https://reviews.llvm.org/D90738