[llvm] cc3bf27 - [RISCV] Remove assertsexti32 from fslw/fsrw isel patterns.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-11-04T11:37:58-08:00
New Revision: cc3bf270776bc362e4a504a2f1bc3c8c932111ea

URL: https://github.com/llvm/llvm-project/commit/cc3bf270776bc362e4a504a2f1bc3c8c932111ea
DIFF: https://github.com/llvm/llvm-project/commit/cc3bf270776bc362e4a504a2f1bc3c8c932111ea.diff

LOG: [RISCV] Remove assertsexti32 from fslw/fsrw isel patterns.

The operations in these patterns shouldn't be effected by sign
bits. And the pattern is starting from a sign_extend_inreg so
we aren't expecting sign bits to be passed through either.

Differential Revision: https://reviews.llvm.org/D90739

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 632e2f0f60312..18abd3bdb6571 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -1024,18 +1024,15 @@ def : Pat<(sra (bitreverse GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 31))>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbt, IsRV64] in {
-def : Pat<(sext_inreg (fshl (assertsexti32 GPR:$rs1),
-                            (shl (assertsexti32 GPR:$rs3), (i64 32)),
-                            (and (assertsexti32 GPR:$rs2), (i64 31))),
+def : Pat<(sext_inreg (fshl GPR:$rs1, (shl GPR:$rs3, (i64 32)),
+                            (and GPR:$rs2, (i64 31))),
                       i32),
           (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs3),
-                            (shl (assertsexti32 GPR:$rs1), (i64 32)),
-                            (or (assertsexti32 GPR:$rs2), (i64 32))),
+def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)),
+                            (or GPR:$rs2, (i64 32))),
                       i32),
           (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs3),
-                            (shl (assertsexti32 GPR:$rs1), (i64 32)),
+def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)),
                             uimm6gt32:$shamt),
                       i32),
           (FSRIW GPR:$rs1, GPR:$rs3, (ImmSub32 uimm6gt32:$shamt))>;