[PATCH] D90735: [RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd47300f503c9: [RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D90735?vs=302740&id=302917#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90735/new/

https://reviews.llvm.org/D90735

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32Zbb.ll
  llvm/test/CodeGen/RISCV/rv32Zbbp.ll
  llvm/test/CodeGen/RISCV/rv32Zbt.ll
  llvm/test/CodeGen/RISCV/rv64Zbt.ll

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