[llvm] 3701e33 - [RISCV] Remove custom isel for (srl (shl val, 32), imm). Use pattern instead. NFCI

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-11-04T09:59:14-08:00
New Revision: 3701e33a2213f2b2307d805bd843656bafcb60cf

URL: https://github.com/llvm/llvm-project/commit/3701e33a2213f2b2307d805bd843656bafcb60cf
DIFF: https://github.com/llvm/llvm-project/commit/3701e33a2213f2b2307d805bd843656bafcb60cf.diff

LOG: [RISCV] Remove custom isel for (srl (shl val, 32), imm). Use pattern instead. NFCI

We don't need custom matching, we just a need a predicate to check
the immediate is greater than 32. We can use the existing ImmSub32
to adjust the immediate.

I've also used the new predicate in the other location that used
ImmSub32. I tried to create a test case where we would break without
the greater than 32 check on that pattern, but DAG combine defeated me.
Still seemed safer to have it.

Differential Revision: https://reviews.llvm.org/D90546

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 641018703e35..853e81ca43ab 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -141,20 +141,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
         return;
       }
     }
-    // Match (srl (shl val, 32), imm).
-    if (Op0->getOpcode() == ISD::SHL &&
-        isa<ConstantSDNode>(Op0->getOperand(1)) &&
-        isa<ConstantSDNode>(Node->getOperand(1))) {
-      uint64_t ShlAmt = Op0->getConstantOperandVal(1);
-      uint64_t SrlAmt = Node->getConstantOperandVal(1);
-      if (ShlAmt == 32 && SrlAmt > 32) {
-        SDValue SrlAmtSub32Val =
-            CurDAG->getTargetConstant(SrlAmt - 32, SDLoc(Node), XLenVT);
-        CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0->getOperand(0),
-                             SrlAmtSub32Val);
-        return;
-      }
-    }
     break;
   }
   case RISCVISD::READ_CYCLE_WIDE:

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 878f7ad5d61d..dde1a15cef2f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -291,6 +291,11 @@ def immbottomxlenset : ImmLeaf<XLenVT, [{
   return countTrailingOnes<uint64_t>(Imm) >= 5;
 }]>;
 
+// A 6-bit constant greater than 32.
+def uimm6gt32 : ImmLeaf<XLenVT, [{
+  return isUInt<6>(Imm) && Imm > 32;
+}]>;
+
 // Addressing modes.
 // Necessary because a frameindex can't be matched directly in a pattern.
 def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>;
@@ -316,6 +321,12 @@ def NegImm : SDNodeXForm<imm, [{
                                    N->getValueType(0));
 }]>;
 
+// Return an immediate value minus 32.
+def ImmSub32 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Formats
 //===----------------------------------------------------------------------===//
@@ -1128,6 +1139,8 @@ def : Pat<(sext_inreg (shl GPR:$rs1, uimm5:$shamt), i32),
           (SLLIW GPR:$rs1, uimm5:$shamt)>;
 // (srl (zexti32 ...), uimm5:$shamt) is matched with custom code due to the
 // need to undo manipulation of the mask value performed by DAGCombine.
+def : Pat<(srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt),
+          (SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
 def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
           (SRAIW GPR:$rs1, uimm5:$shamt)>;
 

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index dc9baf3f12eb..e0a8f72443d8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -40,12 +40,6 @@ def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
   }];
 }
 
-// Return an immediate value minus 32.
-def ImmSub32 : SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N),
-                                   N->getValueType(0));
-}]>;
-
 
 // Convert rotl immediate to a rotr immediate.
 def ImmROTL2R : SDNodeXForm<imm, [{
@@ -1043,9 +1037,9 @@ def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs1),
           (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs1),
                             (shl (assertsexti32 GPR:$rs2), (i64 32)),
-                            uimmlog2xlen:$shamt),
+                            uimm6gt32:$shamt),
                       i32),
-          (FSRIW GPR:$rs1, GPR:$rs2, (ImmSub32 uimm5:$shamt))>;
+          (FSRIW GPR:$rs1, GPR:$rs2, (ImmSub32 uimm6gt32:$shamt))>;
 } // Predicates = [HasStdExtZbt, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {