[llvm] 351c10c - [VE] Add +vpu attribute
Simon Moll via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 4 03:42:25 PST 2020
Author: Simon Moll
Date: 2020-11-04T12:42:00+01:00
New Revision: 351c10cc72143c6ff0b39ce94ddeb0d9f85d2e58
URL: https://github.com/llvm/llvm-project/commit/351c10cc72143c6ff0b39ce94ddeb0d9f85d2e58
DIFF: https://github.com/llvm/llvm-project/commit/351c10cc72143c6ff0b39ce94ddeb0d9f85d2e58.diff
LOG: [VE] Add +vpu attribute
`+vpu` controls whether VEISelLowering adds any vregs. This defaults to
`-vpu` to have scalar code generation out of the box. We bring up
vector isel under the `+vpu` flag. Once vector isel is stable we switch
to `+vpu` and advertise vregs and vops in TTI.
Reviewed By: kaz7
Differential Revision: https://reviews.llvm.org/D90465
Added:
llvm/test/CodeGen/VE/Vector/feature_vpu.ll
Modified:
llvm/lib/Target/VE/VE.td
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.h
llvm/lib/Target/VE/VESubtarget.cpp
llvm/lib/Target/VE/VESubtarget.h
llvm/lib/Target/VE/VETargetTransformInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VE.td b/llvm/lib/Target/VE/VE.td
index 617a6ea458b6..a2c0ba04adaa 100644
--- a/llvm/lib/Target/VE/VE.td
+++ b/llvm/lib/Target/VE/VE.td
@@ -18,6 +18,9 @@ include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// VE Subtarget features.
//
+def FeatureEnableVPU
+ : SubtargetFeature<"vpu", "EnableVPU", "true",
+ "Enable the VPU">;
//===----------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 15bb8e0338cb..c2d8d7341585 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -57,46 +57,48 @@ void VETargetLowering::initRegisterClasses() {
addRegisterClass(MVT::f64, &VE::I64RegClass);
addRegisterClass(MVT::f128, &VE::F128RegClass);
- addRegisterClass(MVT::v2i32, &VE::V64RegClass);
- addRegisterClass(MVT::v4i32, &VE::V64RegClass);
- addRegisterClass(MVT::v8i32, &VE::V64RegClass);
- addRegisterClass(MVT::v16i32, &VE::V64RegClass);
- addRegisterClass(MVT::v32i32, &VE::V64RegClass);
- addRegisterClass(MVT::v64i32, &VE::V64RegClass);
- addRegisterClass(MVT::v128i32, &VE::V64RegClass);
- addRegisterClass(MVT::v256i32, &VE::V64RegClass);
- addRegisterClass(MVT::v512i32, &VE::V64RegClass);
-
- addRegisterClass(MVT::v2i64, &VE::V64RegClass);
- addRegisterClass(MVT::v4i64, &VE::V64RegClass);
- addRegisterClass(MVT::v8i64, &VE::V64RegClass);
- addRegisterClass(MVT::v16i64, &VE::V64RegClass);
- addRegisterClass(MVT::v32i64, &VE::V64RegClass);
- addRegisterClass(MVT::v64i64, &VE::V64RegClass);
- addRegisterClass(MVT::v128i64, &VE::V64RegClass);
- addRegisterClass(MVT::v256i64, &VE::V64RegClass);
-
- addRegisterClass(MVT::v2f32, &VE::V64RegClass);
- addRegisterClass(MVT::v4f32, &VE::V64RegClass);
- addRegisterClass(MVT::v8f32, &VE::V64RegClass);
- addRegisterClass(MVT::v16f32, &VE::V64RegClass);
- addRegisterClass(MVT::v32f32, &VE::V64RegClass);
- addRegisterClass(MVT::v64f32, &VE::V64RegClass);
- addRegisterClass(MVT::v128f32, &VE::V64RegClass);
- addRegisterClass(MVT::v256f32, &VE::V64RegClass);
- addRegisterClass(MVT::v512f32, &VE::V64RegClass);
-
- addRegisterClass(MVT::v2f64, &VE::V64RegClass);
- addRegisterClass(MVT::v4f64, &VE::V64RegClass);
- addRegisterClass(MVT::v8f64, &VE::V64RegClass);
- addRegisterClass(MVT::v16f64, &VE::V64RegClass);
- addRegisterClass(MVT::v32f64, &VE::V64RegClass);
- addRegisterClass(MVT::v64f64, &VE::V64RegClass);
- addRegisterClass(MVT::v128f64, &VE::V64RegClass);
- addRegisterClass(MVT::v256f64, &VE::V64RegClass);
-
- addRegisterClass(MVT::v256i1, &VE::VMRegClass);
- addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
+ if (Subtarget->enableVPU()) {
+ addRegisterClass(MVT::v2i32, &VE::V64RegClass);
+ addRegisterClass(MVT::v4i32, &VE::V64RegClass);
+ addRegisterClass(MVT::v8i32, &VE::V64RegClass);
+ addRegisterClass(MVT::v16i32, &VE::V64RegClass);
+ addRegisterClass(MVT::v32i32, &VE::V64RegClass);
+ addRegisterClass(MVT::v64i32, &VE::V64RegClass);
+ addRegisterClass(MVT::v128i32, &VE::V64RegClass);
+ addRegisterClass(MVT::v256i32, &VE::V64RegClass);
+ addRegisterClass(MVT::v512i32, &VE::V64RegClass);
+
+ addRegisterClass(MVT::v2i64, &VE::V64RegClass);
+ addRegisterClass(MVT::v4i64, &VE::V64RegClass);
+ addRegisterClass(MVT::v8i64, &VE::V64RegClass);
+ addRegisterClass(MVT::v16i64, &VE::V64RegClass);
+ addRegisterClass(MVT::v32i64, &VE::V64RegClass);
+ addRegisterClass(MVT::v64i64, &VE::V64RegClass);
+ addRegisterClass(MVT::v128i64, &VE::V64RegClass);
+ addRegisterClass(MVT::v256i64, &VE::V64RegClass);
+
+ addRegisterClass(MVT::v2f32, &VE::V64RegClass);
+ addRegisterClass(MVT::v4f32, &VE::V64RegClass);
+ addRegisterClass(MVT::v8f32, &VE::V64RegClass);
+ addRegisterClass(MVT::v16f32, &VE::V64RegClass);
+ addRegisterClass(MVT::v32f32, &VE::V64RegClass);
+ addRegisterClass(MVT::v64f32, &VE::V64RegClass);
+ addRegisterClass(MVT::v128f32, &VE::V64RegClass);
+ addRegisterClass(MVT::v256f32, &VE::V64RegClass);
+ addRegisterClass(MVT::v512f32, &VE::V64RegClass);
+
+ addRegisterClass(MVT::v2f64, &VE::V64RegClass);
+ addRegisterClass(MVT::v4f64, &VE::V64RegClass);
+ addRegisterClass(MVT::v8f64, &VE::V64RegClass);
+ addRegisterClass(MVT::v16f64, &VE::V64RegClass);
+ addRegisterClass(MVT::v32f64, &VE::V64RegClass);
+ addRegisterClass(MVT::v64f64, &VE::V64RegClass);
+ addRegisterClass(MVT::v128f64, &VE::V64RegClass);
+ addRegisterClass(MVT::v256f64, &VE::V64RegClass);
+
+ addRegisterClass(MVT::v256i1, &VE::VMRegClass);
+ addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
+ }
}
void VETargetLowering::initSPUActions() {
@@ -262,6 +264,10 @@ void VETargetLowering::initSPUActions() {
/// } Atomic isntructions
}
+void VETargetLowering::initVPUActions() {
+ // TODO upstream vector isel
+}
+
SDValue
VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
bool IsVarArg,
@@ -842,7 +848,7 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
initRegisterClasses();
initSPUActions();
- // TODO initVPUActions();
+ initVPUActions();
setStackPointerRegisterToSaveRestore(VE::SX11);
diff --git a/llvm/lib/Target/VE/VEISelLowering.h b/llvm/lib/Target/VE/VEISelLowering.h
index b2b246c16502..fffb6b5d0497 100644
--- a/llvm/lib/Target/VE/VEISelLowering.h
+++ b/llvm/lib/Target/VE/VEISelLowering.h
@@ -45,7 +45,7 @@ class VETargetLowering : public TargetLowering {
void initRegisterClasses();
void initSPUActions();
- // TODO void initVPUActions();
+ void initVPUActions();
public:
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
diff --git a/llvm/lib/Target/VE/VESubtarget.cpp b/llvm/lib/Target/VE/VESubtarget.cpp
index 6fb699dbdd7a..f9c179e18528 100644
--- a/llvm/lib/Target/VE/VESubtarget.cpp
+++ b/llvm/lib/Target/VE/VESubtarget.cpp
@@ -27,6 +27,9 @@ void VESubtarget::anchor() {}
VESubtarget &VESubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
+ // Default feature settings
+ EnableVPU = false;
+
// Determine default and user specified characteristics
std::string CPUName = std::string(CPU);
if (CPUName.empty())
diff --git a/llvm/lib/Target/VE/VESubtarget.h b/llvm/lib/Target/VE/VESubtarget.h
index f4034df4dce8..04c133342f2a 100644
--- a/llvm/lib/Target/VE/VESubtarget.h
+++ b/llvm/lib/Target/VE/VESubtarget.h
@@ -32,6 +32,13 @@ class VESubtarget : public VEGenSubtargetInfo {
Triple TargetTriple;
virtual void anchor();
+ /// Features {
+
+ // Emit VPU instructions
+ bool EnableVPU;
+
+ /// } Features
+
VEInstrInfo InstrInfo;
VETargetLowering TLInfo;
SelectionDAGTargetInfo TSInfo;
@@ -55,6 +62,8 @@ class VESubtarget : public VEGenSubtargetInfo {
bool enableMachineScheduler() const override;
+ bool enableVPU() const { return EnableVPU; }
+
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
diff --git a/llvm/lib/Target/VE/VETargetTransformInfo.h b/llvm/lib/Target/VE/VETargetTransformInfo.h
index c267c4d9a578..36b283c0e25a 100644
--- a/llvm/lib/Target/VE/VETargetTransformInfo.h
+++ b/llvm/lib/Target/VE/VETargetTransformInfo.h
@@ -33,6 +33,8 @@ class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
const VESubtarget *getST() const { return ST; }
const VETargetLowering *getTLI() const { return TLI; }
+ bool enableVPU() const { return getST()->enableVPU(); }
+
public:
explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
diff --git a/llvm/test/CodeGen/VE/Vector/feature_vpu.ll b/llvm/test/CodeGen/VE/Vector/feature_vpu.ll
new file mode 100644
index 000000000000..c64df5110102
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Vector/feature_vpu.ll
@@ -0,0 +1,5 @@
+; RUN: llc -march=ve -mattr=help 2>&1 > /dev/null | FileCheck %s
+
+; CHECK: Available features for this target:
+; CHECK: vpu - Enable the VPU.
+
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