[PATCH] D90546: [RISCV] Remove custom isel for (srl (shl val, 32), imm). Use pattern instead. NFCI

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:1035
                       i32),
-          (FSRIW GPR:$rs1, GPR:$rs2, (ImmSub32 uimm5:$shamt))>;
+          (FSRIW GPR:$rs1, GPR:$rs2, (ImmSub32 uimm6gt32:$shamt))>;
 } // Predicates = [HasStdExtZbt, IsRV64]
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frasercrmck wrote:
> I might be wrong here, but are we getting the operands to `fshr` the wrong way round? I'm seeing that the intrinsic documentation says that it takes operands `%a, %b` with `%a` in the MSB of the wide value, and we're passing them through to `FSR` as `rs1` and `rs3` respectively, where `rs1` is the LSB of the wide value. I'm reading spec 0.92 so maybe there's a mismatch.
> 
> I don't think this applies to `FSL` because the spec says `rs1` is the MSB of the wide value.
Typical; I just saw D90735. Let's move this discussion over there, then.


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https://reviews.llvm.org/D90546