[PATCH] D90739: [RISCV] Remove assertsexti32 from fslw/fsrw isel patterns.

[Craig Topper via Phabricator via llvm-commits]

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The operations in these patterns shouldn't be effected by sign
bits. And the pattern is starting from a sign_extend_inreg so
we aren't expecting sign bits to be passed through either.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90739

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -1036,18 +1036,15 @@
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbt, IsRV64] in {
-def : Pat<(sext_inreg (fshl (assertsexti32 GPR:$rs1),
-                            (shl (assertsexti32 GPR:$rs3), (i64 32)),
-                            (and (assertsexti32 GPR:$rs2), (i64 31))),
+def : Pat<(sext_inreg (fshl GPR:$rs1, (shl GPR:$rs3, (i64 32)),
+                            (and GPR:$rs2, (i64 31))),
                       i32),
           (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs3),
-                            (shl (assertsexti32 GPR:$rs1), (i64 32)),
-                            (or (assertsexti32 GPR:$rs2), (i64 32))),
+def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)),
+                            (or GPR:$rs2, (i64 32))),
                       i32),
           (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs3),
-                            (shl (assertsexti32 GPR:$rs1), (i64 32)),
+def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)),
                             uimmlog2xlen:$shamt),
                       i32),
           (FSRIW GPR:$rs1, GPR:$rs3, (ImmSub32 uimm5:$shamt))>;


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