[PATCH] D90738: [RISCV] Support Zfh half-precision floating-point extension.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
HsiangKai added reviewers: evandro, craig.topper, asb, lenary, luismarques.
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Support "Zfh" extension according to https://github.com/riscv/riscv-isa-manual/blob/zfh/src/zfh.tex.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90738

Files:
  llvm/include/llvm/IR/RuntimeLibcalls.def
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/half-arith.ll
  llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/half-br-fcmp.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-fcmp.ll
  llvm/test/CodeGen/RISCV/half-imm.ll
  llvm/test/CodeGen/RISCV/half-intrinsics.ll
  llvm/test/CodeGen/RISCV/half-isnan.ll
  llvm/test/CodeGen/RISCV/half-mem.ll
  llvm/test/CodeGen/RISCV/half-select-fcmp.ll
  llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
  llvm/test/CodeGen/RISCV/rv64f-half-convert.ll
  llvm/test/CodeGen/RISCV/zfh-imm.ll
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zfh-invalid.s
  llvm/test/MC/RISCV/rv32zfh-valid.s
  llvm/test/MC/RISCV/rv64zfh-invalid.s
  llvm/test/MC/RISCV/rv64zfh-valid.s
  llvm/test/MC/RISCV/rvzfh-aliases-valid.s
  llvm/test/MC/RISCV/rvzfh-pseudos.s

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