[PATCH] D89084: [PowerPC] Combine select_cc (x, 0, t, f, lt) to avoid generating `isel`

Tue Nov 3 21:26:26 PST 2020

lkail added a comment.

In D89084#2352644 <https://reviews.llvm.org/D89084#2352644>, @shchenz wrote:

> I guess this opt should also be profitable for opcode `SELECT`, is there any reason we don't do this?

The complete form of `select` is `select cond, true_value, false_value` and `cond` usually comes from comparison. Most comparisons can't be transformed to shift ops easily. For current ppc backend without this ptch, such pattern is transformed into a `select_cc` node before pattern-matching instruction selector.

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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13599
+  // where (z - y) is power of 2.
+  if (VT.isInteger() && TrueC && FalseC && isTypeLegal(VT) &&
+      (isNullConstant(RHS) && CC == ISD::SETLT)) {
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shchenz wrote:
> is it possible to put some conditions in early returns and put some comments there?
Well, it might require some refactor work if adding more `select_cc` related patterns.

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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13614
+                      DAG.getConstant(SignBitShiftAmount, DL, CompVT));
+      if (CompVT.getSizeInBits() < VT.getSizeInBits())
+        SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SignBit);
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shchenz wrote:
> can `getZExtOrTrunc` be used here?
Good one.

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