[PATCH] D90699: [AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD.

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added a reviewer: paquette.
aemerson added a project: LLVM.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka.
aemerson requested review of this revision.

For the <2 x float> case, instead of adding another combine or legalization to get it into a <4 x float> form, I'm just adding a GISel specific selection pattern to cover it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90699

Files:
  llvm/lib/Target/AArch64/AArch64Combine.td
  llvm/lib/Target/AArch64/AArch64InstrGISel.td
  llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir

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