[PATCH] D89576: [SVE][CodeGen] Lower scalable masked scatters

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin updated this revision to Diff 302587.
kmclaughlin marked 3 inline comments as done.
kmclaughlin added a comment.

- Changed `isLegalMaskedGSIndexType` to return true if the instruction can perform the sign extend (i.e. if the index is extended from i32 and the number of elements is at least 4)
- Added `getCanonicalIndexType` to convert redundant addressing modes (e.g. scaling is redundant when accessing bytes)
- Added a target-specific DAG combine for mscatter to promote indices smaller than i32
- Added various tests for type legalisation in `sve-masked-scatter-legalise.ll`


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89576/new/

https://reviews.llvm.org/D89576

Files:
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-masked-scatter-32b-scaled.ll
  llvm/test/CodeGen/AArch64/sve-masked-scatter-32b-unscaled.ll
  llvm/test/CodeGen/AArch64/sve-masked-scatter-64b-scaled.ll
  llvm/test/CodeGen/AArch64/sve-masked-scatter-64b-unscaled.ll
  llvm/test/CodeGen/AArch64/sve-masked-scatter-legalise.ll

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