[PATCH] D90607: [AMDGPU] Fix ds_read2/write2 with unaligned offsets

Tue Nov 3 06:43:51 PST 2020

foad marked 2 inline comments as done.
foad added a comment.

In D90607#2368689 <https://reviews.llvm.org/D90607#2368689>, @arsenm wrote:

> Does the GlobalISel pattern have the same problem?

No, it had a different one :) For read2/write2_b64 it was passing 16 in as the last argument to isDSOffsetLegal, which is the bit width of the "offset" fields in the instruction. I think it's all good now.

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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1262
   SDLoc DL(Addr);
   unsigned Align = IsDS128 ? 8 : 4;

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arsenm wrote:
> I think the variable name align here is misleading since this isn't the memory alignment
I used `Size` for the size in bytes of each of the 2 accesses.

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  https://reviews.llvm.org/D90607/new/

https://reviews.llvm.org/D90607