[llvm] 6e008cb - [AMDGPU] Precommit globalisel tests for ds_read2_b64 with large offset

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2020-11-03T14:38:56Z
New Revision: 6e008cb554b3bd737834d55bc2158545d7072973

URL: https://github.com/llvm/llvm-project/commit/6e008cb554b3bd737834d55bc2158545d7072973
DIFF: https://github.com/llvm/llvm-project/commit/6e008cb554b3bd737834d55bc2158545d7072973.diff

LOG: [AMDGPU] Precommit globalisel tests for ds_read2_b64 with large offset

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
index b71a311b7545..a844c391f42b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -amdgpu-global-isel-new-legality -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
 # RUN: llc -amdgpu-global-isel-new-legality -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
 
@@ -59,6 +60,66 @@ body: |
 
 ---
 
+name: load_local_v4s32_align_8_offset_160
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins:  $vgpr0
+
+    ; GFX7-LABEL: name: load_local_v4s32_align_8_offset_160
+    ; GFX7: liveins: $vgpr0
+    ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX7: $m0 = S_MOV_B32 -1
+    ; GFX7: [[DS_READ2_B64_:%[0-9]+]]:vreg_128 = DS_READ2_B64 [[COPY]], 50, 51, 0, implicit $m0, implicit $exec :: (load 16, align 8, addrspace 3)
+    ; GFX7: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DS_READ2_B64_]]
+    ; GFX9-LABEL: name: load_local_v4s32_align_8_offset_160
+    ; GFX9: liveins: $vgpr0
+    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX9: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128 = DS_READ_B128_gfx9 [[COPY]], 400, 0, implicit $exec :: (load 16, align 8, addrspace 3)
+    ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DS_READ_B128_gfx9_]]
+    %0:vgpr(p3) = COPY $vgpr0
+    %1:vgpr(s32) = G_CONSTANT i32 400
+    %2:vgpr(p3) = G_PTR_ADD %0, %1
+    %3:vgpr(<4 x  s32>) = G_LOAD %2 :: (load 16, align 8, addrspace 3)
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
+
+...
+
+---
+
+name: load_local_v4s32_align_8_offset_320
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins:  $vgpr0
+
+    ; GFX7-LABEL: name: load_local_v4s32_align_8_offset_320
+    ; GFX7: liveins: $vgpr0
+    ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX7: $m0 = S_MOV_B32 -1
+    ; GFX7: [[DS_READ2_B64_:%[0-9]+]]:vreg_128 = DS_READ2_B64 [[COPY]], 500, 501, 0, implicit $m0, implicit $exec :: (load 16, align 8, addrspace 3)
+    ; GFX7: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DS_READ2_B64_]]
+    ; GFX9-LABEL: name: load_local_v4s32_align_8_offset_320
+    ; GFX9: liveins: $vgpr0
+    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX9: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128 = DS_READ_B128_gfx9 [[COPY]], 4000, 0, implicit $exec :: (load 16, align 8, addrspace 3)
+    ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DS_READ_B128_gfx9_]]
+    %0:vgpr(p3) = COPY $vgpr0
+    %1:vgpr(s32) = G_CONSTANT i32 4000
+    %2:vgpr(p3) = G_PTR_ADD %0, %1
+    %3:vgpr(<4 x  s32>) = G_LOAD %2 :: (load 16, align 8, addrspace 3)
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
+
+...
+
+---
+
 name: load_local_v2s64
 legalized:       true
 regBankSelected: true