[PATCH] D86519: [SystemZ] New pass for domain reassignment from integer to vector.
Jonas Paulsson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 3 04:08:35 PST 2020
jonpa updated this revision to Diff 302539.
jonpa added a comment.
Patch still experimental.
Tried
- Isolate loops so that closures with instruction inside them are reassigned only when necessary inside the loop.
- Don't load extra immediate operands in tiny blocks.
Saw no difference on benchmarks with these and other experiments...
In order to get some kind of idea of the success of this patch, I improved the debug dumping so that the reasons for not being able to reassign a closure is given explicitly at the point of high register pressure. With this, closures that really would have been reassigned based on register pressure but were not can be categorized (as opposed to just looking at all illegal closures). The results are:
Number of closures reassigned: 17209
Number of closures not reassigned when deemed needed: 288869
=> Only 6% successfully reassigned
Reasons:
Address : 118922 41% (Out of the 289k)
Physreg : 73828 25%
Interfering call : 47629 17%
RISBGN : 27953 10%
INSERT_SUBREG : 14650 5% (Probably involves quite some work to handle subreg cases)
Insertion(s) needed : 11762 4%
CR : 3718
CGR : 2352
Address or Physreg : 183395 63%
Addr/PhysReg/Call : 206325 71%
Physreg or Call : 100860 35%
RISBGN, no a/p/c : 18375 6%
Ideas to try next:
- Part of the address register operands is due to LA/LAY being used for addition. It could be worth trying to handle those cases.
- RISBGN:
RISBGN operands:
... Steps rotated High bit I4 Interpretation Reassignment
3503 29, 188, 3 5% 3 1
4117 1, 189, 0 6% 0 1
4389 63, 191, 0 6% 0 1 copy 63:63, "zero extend LSB" mask + VN ?
8903 32, 189, 0 13% 0 1 "Zero hi32, copy 32:61"
21666 62, 191, 0 31% 0 1 "zero extend two lowermost bits" mask + VN ?
- Register compares (CR/CGR)
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D86519/new/
https://reviews.llvm.org/D86519
Files:
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/SystemZ/CMakeLists.txt
llvm/lib/Target/SystemZ/SystemZ.h
llvm/lib/Target/SystemZ/SystemZDomainReassignment.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.h
llvm/lib/Target/SystemZ/SystemZInstrVector.td
llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
llvm/test/CodeGen/SystemZ/buildvector-00.ll
llvm/test/CodeGen/SystemZ/dag-combine-01.ll
llvm/test/CodeGen/SystemZ/dag-combine-03.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-01.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-02.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-03.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-04.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-05.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-06.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-07.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-08.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-09.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-10.mir
llvm/test/CodeGen/SystemZ/domain-reassignment-11.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-12.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-13.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-14.ll
llvm/test/CodeGen/SystemZ/knownbits.ll
llvm/test/CodeGen/SystemZ/stack-clash-protection.ll
llvm/test/CodeGen/SystemZ/subregliveness-04.ll
llvm/test/CodeGen/SystemZ/tls-08.ll
llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
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