[PATCH] D89090: [RISCV] Only return DestSourcePair from isCopyInstrImpl for registers

[Jessica Clarke via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7601a2173893: [RISCV] Only return DestSourcePair from isCopyInstrImpl for registers (authored by jrtc27).
Herald added subscribers: frasercrmck, NickHung.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89090/new/

https://reviews.llvm.org/D89090

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/copy-frameindex.mir


Index: llvm/test/CodeGen/RISCV/copy-frameindex.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/copy-frameindex.mir
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -debugify-and-strip-all-safe -run-pass machine-sink %s -o - 2>&1 | FileCheck %s
+
+--- |
+  define void @sink_addi_fi(i32 %0) !dbg !5 {
+  bb.0:
+    %1 = alloca i32, align 4
+    call void @llvm.dbg.value(metadata i32* %1, metadata !1, metadata !DIExpression()), !dbg !3
+    %2 = icmp eq i32 %0, 0
+    br i1 %2, label %bb.2, label %bb.1
+  bb.1:
+    store volatile i32 0, i32* %1, align 4
+    br label %bb.2
+  bb.2:
+    ret void
+  }
+
+  declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+  !llvm.dbg.cu = !{!0}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4)
+  !1 = !DILocalVariable(name: "var", scope: !5, file: !4, line: 2, type: !2)
+  !2 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
+  !3 = !DILocation(line: 0, scope: !5)
+  !4 = !DIFile(filename: "test.c", directory: "")
+  !5 = distinct !DISubprogram(name: "sink_addi_fi", scope: !4, file: !4, line: 1, type: !6, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !8)
+  !6 = !DISubroutineType(types: !7)
+  !7 = !{null, !2}
+  !8 = !{}
+
+...
+---
+name: sink_addi_fi
+liveins:
+  - { reg: '$x10', virtual-reg: '%0' }
+stack:
+  - { id: 0, offset: 0, size: 4, alignment: 4 }
+body: |
+  ; CHECK-LABEL: name: sink_addi_fi
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr = COPY $x10
+  ; CHECK:   BEQ killed [[COPY]], $x0, %bb.2
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0
+  ; CHECK:   SW $x0, killed [[ADDI]], 0 :: (volatile store 4 into %stack.0)
+  ; CHECK: bb.2:
+  ; CHECK:   PseudoRET
+  bb.0:
+    liveins: $x10
+    %0:gpr = COPY $x10
+    DBG_VALUE %stack.0, $noreg, !1, !DIExpression(), debug-location !3
+    %1:gpr = ADDI %stack.0, 0
+    DBG_VALUE %1, $noreg, !1, !DIExpression(DW_OP_plus_uconst, 0, DW_OP_stack_value), debug-location !3
+    BEQ killed %0:gpr, $x0, %bb.2
+  bb.1:
+    SW $x0, killed %1:gpr, 0 :: (volatile store 4 into %stack.0, align 4)
+  bb.2:
+    PseudoRET
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -538,7 +538,9 @@
   default:
     break;
   case RISCV::ADDI:
-    if (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
+    // Operand 1 can be a frameindex but callers expect registers
+    if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
+        MI.getOperand(2).getImm() == 0)
       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
     break;
   case RISCV::FSGNJ_D:


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