[PATCH] D90607: [AMDGPU] Fix ds_read2/write2 with unaligned offsets

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Does the GlobalISel pattern have the same problem?



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1262
   SDLoc DL(Addr);
   unsigned Align = IsDS128 ? 8 : 4;
 
----------------
I think the variable name align here is misleading since this isn't the memory alignment


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1270-1272
+    bool OffsetIsAligned = Align * OffsetValue0 == C1->getZExtValue();
     // (add n0, c0)
+    if (isDSOffsetLegal(N0, OffsetValue1, 8) && OffsetIsAligned) {
----------------
split this into a isDSOffset2Legal function?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90607/new/

https://reviews.llvm.org/D90607