[PATCH] D90605: [llvm][AArch64] Simplify (and (sign_extend..) #bitmask).

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli created this revision.
fpetrogalli added reviewers: peterwaller-arm, samparker, efriedma.
Herald added subscribers: llvm-commits, ecnelises, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
fpetrogalli requested review of this revision.

Fold

  VT = (and (sign_extend NarrowVT to VT) #bitmask)

into

  VT = (zero_extend NarrowVT)

With this combine, the test replaces a sign extended load + an
unsigned extention with a zero extended load to render one of the
operands of the last multiplication.

  BEFORE                       |  AFTER
    f_i16_i32:                 |    f_i16_i32:
         .fnstart              |           .fnstart
         ldrsh   r0, [r0]      |           ldrh    r1, [r1]
         ldrsh   r1, [r1]      |           ldrsh   r0, [r0]
         smulbb  r0, r1, r0    |           smulbb  r0, r0, r1
         uxth    r1, r1        |           mul     r0, r0, r1
         mul     r0, r0, r1    |           bx      lr
         bx      lr            |


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90605

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
  llvm/test/CodeGen/ARM/and-sext-combine.ll

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