[PATCH] D90092: [AVR] Optimize 16-bit int shift

Mon Nov 2 05:27:15 PST 2020

benshi001 added a comment.

In D90092#2366711 <https://reviews.llvm.org/D90092#2366711>, @aykevl wrote:

> See my comment D89047#2366709 <https://reviews.llvm.org/D89047#2366709>.
> I think this optimization would be implemented better in SelectionDAG instead of using pseudo-instructions. That would also make it possible to optimize things like `(short)x << 12`.

Could you please explain more about `be implemented better in SelectionDAG instead of using pseudo-instructions` ? I can not figure out a way using SelectionDAG. Because I think SelectionDAG requires data flow dependency and looks like a tree structure. But The mov/clr pair seems can not be put into  a tree structure.

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