[PATCH] D89956: [AArch64] Redundant masks in downcast long multiply

[Nicholas Guy via Phabricator via llvm-commits]

NickGuy updated this revision to Diff 302229.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89956/new/

https://reviews.llvm.org/D89956

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll


Index: llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s
+
+define i64 @umull(i64 %x0, i64 %x1) {
+; CHECK-LABEL: umull:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umull x0, w1, w0
+; CHECK-NEXT:    ret
+entry:
+  %and = and i64 %x0, 4294967295
+  %and1 = and i64 %x1, 4294967295
+  %mul = mul nuw i64 %and1, %and
+  ret i64 %mul
+}
+
+define i64 @smull(i64 %x0, i64 %x1) {
+; CHECK-LABEL: smull:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull x0, w1, w0
+; CHECK-NEXT:    ret
+entry:
+  %sext = shl i64 %x0, 32
+  %conv1 = ashr exact i64 %sext, 32
+  %sext4 = shl i64 %x1, 32
+  %conv3 = ashr exact i64 %sext4, 32
+  %mul = mul nsw i64 %conv3, %conv1
+  ret i64 %mul
+}
+
+define i64 @smull_and_zext(i64 %x, i32 %y) {
+; CHECK-LABEL: smull_and_zext:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull x0, w0, w1
+; CHECK-NEXT:    ret
+entry:
+  %and = and i64 %x, 4294967295
+  %conv = zext i32 %y to i64
+  %mul = mul nuw nsw i64 %and, %conv
+  ret i64 %mul
+}
\ No newline at end of file
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1475,6 +1475,17 @@
 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
 
+def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (sext_inreg GPR64:$Rm, i32))),
+          (SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
+
+def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (sext GPR32:$Rm))),
+          (SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
+def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (zext GPR32:$Rm))),
+          (SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
+
+def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (and GPR64:$Rm, 0xFFFFFFFF))),
+          (UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
+
 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
           (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),


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