[PATCH] D90580: [RISCV] When matching RORIW, make sure the same input is given to both shifts.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

The comment at the top of `SelectRORIW` says

  //  (SIGN_EXTEND_INREG (OR (SHL (AsserSext RS1, i32), VC2),
  //                         (SRL (AND (AssertSext RS2, i32), VC3), VC1)))

should it make it apparent that RS1 must equal RS2?

LGTM otherwise.



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Comment at: llvm/test/CodeGen/RISCV/rv64Zbbp.ll:346
 
 ; This test is similar to the type legalized versio of the fshl/fshr tests, but
 ; instead of having the same input to both shifts it has different inputs. Make
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You could fix up the typo `versio` here, and `has a roriw` below.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D90580