[PATCH] D90092: [AVR] Optimize 16-bit int shift

Sun Nov 1 08:24:42 PST 2020

benshi001 added a comment.

In D90092#2366711 <https://reviews.llvm.org/D90092#2366711>, @aykevl wrote:

> See my comment D89047#2366709 <https://reviews.llvm.org/D89047#2366709>.
> I think this optimization would be implemented better in SelectionDAG instead of using pseudo-instructions. That would also make it possible to optimize things like `(short)x << 12`.

Thanks. I would try to improve my patch by

1. introducing AVRISD:LSL4/SLR4/ASR4/LSL12/SLR12/ASR12,
2. avoid using pseudo instructions.

The above ways can optimize most cases, except for shiftAmount = 3 and shiftAmount = 15. However I would like to handle these corner cases in another patch.

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