[llvm] ef6f6d1 - [TableGen] Eliminate uses of true and false in .td files.

[Paul C. Anagnostopoulos via llvm-commits]

Author: Paul C. Anagnostopoulos
Date: 2020-10-31T10:54:33-04:00
New Revision: ef6f6d1c1a2819407c8c218119b97e1e656e5ef3

URL: https://github.com/llvm/llvm-project/commit/ef6f6d1c1a2819407c8c218119b97e1e656e5ef3
DIFF: https://github.com/llvm/llvm-project/commit/ef6f6d1c1a2819407c8c218119b97e1e656e5ef3.diff

LOG: [TableGen] Eliminate uses of true and false in .td files.

They occurred in one NVPTX file and some test files.

Differential Revision: https://reviews.llvm.org/D90513

Added: 
    

Modified: 
    llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    llvm/test/TableGen/cond-empty-list-arg.td
    llvm/test/TableGen/condsbit.td
    llvm/test/TableGen/if.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index fe7a84f9a361..6bb8dc6aebf8 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -137,7 +137,7 @@ def do_SQRTF32_RN : Predicate<"usePrecSqrtF32()">;
 def hasHWROT32 : Predicate<"Subtarget->hasHWROT32()">;
 def noHWROT32 : Predicate<"!Subtarget->hasHWROT32()">;
 
-def true : Predicate<"true">;
+def True : Predicate<"true">;
 
 def hasPTX31 : Predicate<"Subtarget->getPTXVersion() >= 31">;
 def hasPTX60 : Predicate<"Subtarget->getPTXVersion() >= 60">;
@@ -1022,12 +1022,12 @@ multiclass FMA_F16<string OpcStr, RegisterClass RC, Predicate Pred> {
 }
 
 defm FMA16_ftz : FMA_F16<"fma.rn.ftz.f16", Float16Regs, doF32FTZ>;
-defm FMA16     : FMA_F16<"fma.rn.f16", Float16Regs, true>;
+defm FMA16     : FMA_F16<"fma.rn.f16", Float16Regs, True>;
 defm FMA16x2_ftz : FMA_F16<"fma.rn.ftz.f16x2", Float16x2Regs, doF32FTZ>;
-defm FMA16x2     : FMA_F16<"fma.rn.f16x2", Float16x2Regs, true>;
+defm FMA16x2     : FMA_F16<"fma.rn.f16x2", Float16x2Regs, True>;
 defm FMA32_ftz : FMA<"fma.rn.ftz.f32", Float32Regs, f32imm, doF32FTZ>;
-defm FMA32     : FMA<"fma.rn.f32", Float32Regs, f32imm, true>;
-defm FMA64     : FMA<"fma.rn.f64", Float64Regs, f64imm, true>;
+defm FMA32     : FMA<"fma.rn.f32", Float32Regs, f32imm, True>;
+defm FMA64     : FMA<"fma.rn.f64", Float64Regs, f64imm, True>;
 
 // sin/cos
 def SINF:  NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),

diff  --git a/llvm/test/TableGen/cond-empty-list-arg.td b/llvm/test/TableGen/cond-empty-list-arg.td
index 5f4ccade1697..990efbd1a7aa 100644
--- a/llvm/test/TableGen/cond-empty-list-arg.td
+++ b/llvm/test/TableGen/cond-empty-list-arg.td
@@ -1,8 +1,22 @@
-// RUN: llvm-tblgen %s
+// RUN: llvm-tblgen %s | FileCheck %s
 // XFAIL: vg_leak
 
+// Check that !cond works with an empty list value.
+
 class C<bit cond> {
-  bit true = 1;
-  list<int> X = !cond(cond: [1, 2, 3], true : []);
-  list<int> Y = !cond(cond: [], true : [4, 5, 6]);
+  bit True = 1;
+  list<int> X = !cond(cond: [1, 2, 3], True : []);
+  list<int> Y = !cond(cond: [], True : [4, 5, 6]);
 }
+
+// CHECK: def rec1
+// CHECK:   X = [];
+// CHECK:   Y = [4, 5, 6];
+
+def rec1 : C<0>;
+
+// CHECK: def rec2
+// CHECK:   X = [1, 2, 3];
+// CHECK:   Y = [];
+
+def rec2 : C<1>;

diff  --git a/llvm/test/TableGen/condsbit.td b/llvm/test/TableGen/condsbit.td
index e08ac97f68bf..1409c0a6b6c6 100644
--- a/llvm/test/TableGen/condsbit.td
+++ b/llvm/test/TableGen/condsbit.td
@@ -1,14 +1,16 @@
-// check that !cond works well with bit conditional values
 // RUN: llvm-tblgen %s | FileCheck %s
 // XFAIL: vg_leak
+
+// Check that !cond works well with bit conditional values.
+
 // CHECK: a = 6
 // CHECK: a = 5
 
 class A<bit b = 1> {
-  bit true = 1;
-  int a = !cond(b: 5, true : 6);
-  bit c = !cond(b: 0, true : 1);
-  bits<1> d = !cond(b: 0, true : 1);
+  bit True = 1;
+  int a = !cond(b: 5, True : 6);
+  bit c = !cond(b: 0, True : 1);
+  bits<1> d = !cond(b: 0, True : 1);
 }
 
 def X : A<0>;

diff  --git a/llvm/test/TableGen/if.td b/llvm/test/TableGen/if.td
index a3148494dd13..b2ba89c8dd08 100644
--- a/llvm/test/TableGen/if.td
+++ b/llvm/test/TableGen/if.td
@@ -110,14 +110,14 @@ def EXd2 : EX<0, E1d, E2d>;
 // CHECK: Result2d = "OK"
 
 def Not1 {
-  bit true = 1;
-  string Result1a = !if(true, "OK", "not OK");
-  string Result1b = !if(!not(true), "not OK", "OK");
-
-  bit false = 0;
-  string Result1c = !if(false, "not OK", "OK");
-  string Result1d = !if(!not(false), "OK", "not OK");
-  string Result1e = !if(!not(!not(false)), "not OK", "OK");
+  bit True = 1;
+  string Result1a = !if(True, "OK", "not OK");
+  string Result1b = !if(!not(True), "not OK", "OK");
+
+  bit False = 0;
+  string Result1c = !if(False, "not OK", "OK");
+  string Result1d = !if(!not(False), "OK", "not OK");
+  string Result1e = !if(!not(!not(False)), "not OK", "OK");
 }
 
 def Not2 {