[llvm] 39f77b3 - [X86] assignValueToReg - fix Wshadow warning. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-10-31T11:39:26Z
New Revision: 39f77b3224c6ea4bd87e72c407983e237bdacf1d

URL: https://github.com/llvm/llvm-project/commit/39f77b3224c6ea4bd87e72c407983e237bdacf1d
DIFF: https://github.com/llvm/llvm-project/commit/39f77b3224c6ea4bd87e72c407983e237bdacf1d.diff

LOG: [X86] assignValueToReg - fix Wshadow warning. NFCI.

X86OutgoingValueHandler already has a MIB member

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86CallLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86CallLowering.cpp b/llvm/lib/Target/X86/X86CallLowering.cpp
index 8342cad45dfd..bfb7d4ee79e8 100644
--- a/llvm/lib/Target/X86/X86CallLowering.cpp
+++ b/llvm/lib/Target/X86/X86CallLowering.cpp
@@ -134,9 +134,10 @@ struct X86OutgoingValueHandler : public CallLowering::IncomingValueHandler {
     unsigned ValSize = VA.getValVT().getSizeInBits();
     unsigned LocSize = VA.getLocVT().getSizeInBits();
     if (PhysRegSize > ValSize && LocSize == ValSize) {
-      assert((PhysRegSize == 128 || PhysRegSize == 80)  && "We expect that to be 128 bit");
-      auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
-      ExtReg = MIB.getReg(0);
+      assert((PhysRegSize == 128 || PhysRegSize == 80) &&
+             "We expect that to be 128 bit");
+      ExtReg =
+          MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg).getReg(0);
     } else
       ExtReg = extendRegister(ValVReg, VA);