[PATCH] D90479: [WIP][ValueTracking] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/Transforms/InstCombine/and2.ll:155
+; CHECK-NEXT:    ret i8 [[SH]]
 ;
   %sh = lshr i8 1, %x
----------------
These tests look like they might even need to be scrapped? And we just limit the transform to Shl instead of logical shifts in general.


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Comment at: llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll:191
 ;
   %lshr = lshr i32 12345, %y
   %and = and i32 %lshr, 4294967288  ; ~7
----------------
Replace with -12345 so we don't have leading zeroes?


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Comment at: llvm/test/Transforms/InstCombine/signbit-shl-and-icmpeq-zero.ll:190
 ; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_X_is_constant1(
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]]
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], 12345
----------------
Replace with -2147483649 so we don't have trailing zeroes?


Repository:
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  https://reviews.llvm.org/D90479/new/

https://reviews.llvm.org/D90479