[llvm] 790f577 - AMDGPU: Fix missing writelane cases to skip with exec=0

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-10-30T11:15:11-04:00
New Revision: 790f5771fd00e18e7eae7f9649ab529c20dd7823

URL: https://github.com/llvm/llvm-project/commit/790f5771fd00e18e7eae7f9649ab529c20dd7823
DIFF: https://github.com/llvm/llvm-project/commit/790f5771fd00e18e7eae7f9649ab529c20dd7823.diff

LOG: AMDGPU: Fix missing writelane cases to skip with exec=0

Added: 
    llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-mode-def.mir


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 8bfe028b1768..edba266586b3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3108,7 +3108,8 @@ bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
   //
   // However, executing them with EXEC = 0 causes them to operate on undefined
   // data, which we avoid by returning true here.
-  if (Opcode == AMDGPU::V_READFIRSTLANE_B32 || Opcode == AMDGPU::V_READLANE_B32)
+  if (Opcode == AMDGPU::V_READFIRSTLANE_B32 ||
+      Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32)
     return true;
 
   return false;

diff  --git a/llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-mode-def.mir b/llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
similarity index 71%
rename from llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-mode-def.mir
rename to llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
index 3f2788d81899..ee72fa99a129 100644
--- a/llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-mode-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
@@ -109,3 +109,56 @@ body: |
   bb.2:
     S_ENDPGM 0
 ...
+
+---
+
+name: need_skip_writelane_b32
+body: |
+  ; CHECK-LABEL: name: need_skip_writelane_b32
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   $sgpr0 = IMPLICIT_DEF
+  ; CHECK:   $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0
+  ; CHECK: bb.2:
+  ; CHECK:   S_ENDPGM 0
+  bb.0:
+    successors: %bb.1, %bb.2
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
+
+  bb.1:
+    successors: %bb.2
+    $sgpr0 = IMPLICIT_DEF
+    $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0
+
+  bb.2:
+    S_ENDPGM 0
+...
+
+---
+name: need_skip_readlane_b32
+body: |
+  ; CHECK-LABEL: name: need_skip_readlane_b32
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   $vgpr0 = IMPLICIT_DEF
+  ; CHECK:   $sgpr0 = V_READLANE_B32 $vgpr0, 0
+  ; CHECK: bb.2:
+  ; CHECK:   S_ENDPGM 0
+  bb.0:
+    successors: %bb.1, %bb.2
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
+
+  bb.1:
+    successors: %bb.2
+    $vgpr0 = IMPLICIT_DEF
+    $sgpr0 = V_READLANE_B32 $vgpr0, 0
+
+  bb.2:
+    S_ENDPGM 0
+...