[PATCH] D90462: [VE][TTI] don't advertise vregs/vops

[Simon Moll via Phabricator via llvm-commits]

simoll created this revision.
simoll added reviewers: kaz7, k-ishizaka.
simoll added a project: VE.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.
simoll requested review of this revision.

Claim to not have any vector support to dissuade SLP, LV and friends from generating SIMD IR for the VE target.
We will take this back once vector isel is stable.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90462

Files:
  llvm/lib/Target/VE/VETargetTransformInfo.h


Index: llvm/lib/Target/VE/VETargetTransformInfo.h
===================================================================
--- llvm/lib/Target/VE/VETargetTransformInfo.h
+++ llvm/lib/Target/VE/VETargetTransformInfo.h
@@ -38,11 +38,45 @@
       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
         TLI(ST->getTargetLowering()) {}
 
-  unsigned getNumberOfRegisters(unsigned ClassID) const { return 64; }
+  unsigned getNumberOfRegisters(unsigned ClassID) const {
+    bool VectorRegs = (ClassID == 1);
+    if (VectorRegs) {
+      // TODO report vregs once vector isel is stable.
+      return 0;
+    }
 
-  unsigned getRegisterBitWidth(bool Vector) const { return 64; }
+    return 64;
+  }
 
-  unsigned getMinVectorRegisterBitWidth() const { return 64; }
+  unsigned getRegisterBitWidth(bool Vector) const {
+    if (Vector) {
+      // TODO report vregs once vector isel is stable.
+      return 0;
+    }
+    return 64;
+  }
+
+  unsigned getMinVectorRegisterBitWidth() const {
+    // TODO report vregs once vector isel is stable.
+    return 0;
+  }
+
+  /// Load & Store {
+  bool isLegalMaskedLoad(Type *DataType, MaybeAlign Alignment) { return false; }
+  bool isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) {
+    return false;
+  }
+  bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment) {
+    return false;
+  };
+  bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) {
+    return false;
+  }
+  /// } Load & Store
+
+  /// Reductions {
+  bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
+  /// } Reductions
 };
 
 } // namespace llvm


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