[PATCH] D90404: [AMDGPU] Add alignment check for v3 to v4 load type promotion

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas updated this revision to Diff 301824.
cdevadas edited the summary of this revision.
cdevadas added a comment.

Made the alignment check to 8-byte boundary instead of 16-byte.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90404/new/

https://reviews.llvm.org/D90404

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/bfi_int.ll
  llvm/test/CodeGen/AMDGPU/fshl.ll
  llvm/test/CodeGen/AMDGPU/fshr.ll
  llvm/test/CodeGen/AMDGPU/kernel-args.ll
  llvm/test/CodeGen/AMDGPU/merge-stores.ll
  llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
  llvm/test/CodeGen/AMDGPU/sign_extend.ll
  llvm/test/CodeGen/AMDGPU/store-local.96.ll
  llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll

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