[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

Thu Oct 29 23:58:00 PDT 2020

Elvina marked 6 inline comments as done.
Elvina added inline comments.

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Comment at: clang/test/Driver/aarch64-cpus.c:298

+// RUN: %clang -target aarch64 -mcpu=tsv110 -### -c %s 2>&1 | FileCheck -check-prefix=TSV110 %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=tsv110 -### -c %s 2>&1 | FileCheck -check-prefix=TSV110 %s
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SjoerdMeijer wrote:
> This is unrelated to the scheduling model. 
> Looks like good tests to me, so please go ahead and commit this separately, no need for another review.
Will do, thanks

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Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110Details.td:1
+//==- AArch64SchedTSV110Details.td - TSV110 Scheduling Defs -*- tablegen -*-==//
+//
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SjoerdMeijer wrote:
> Just a nit/question on this new file: is there a benefit of having this separately? If there's none, just merge into  AArch64SchedTSV110.td, as that would be more consistent with other schedmodels?
No specific needs to do this, so  I'll merge all into one file.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D89972/new/

https://reviews.llvm.org/D89972