[PATCH] D90339: [RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 29 14:53:47 PDT 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rG74b078294ff9: [RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW (authored by craig.topper).
Herald added subscribers: frasercrmck, jrtc27.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90339/new/
https://reviews.llvm.org/D90339
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
Index: llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
+++ llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
@@ -14,8 +14,6 @@
; CHECK-NEXT: mul a0, a0, a0
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: addi a0, a0, 1
-; CHECK-NEXT: slli a1, a1, 32
-; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: sllw a0, a0, a1
; CHECK-NEXT: ret
%b = mul i32 %x, %x
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1071,9 +1071,12 @@
SDValue RHS = N->getOperand(1);
APInt LHSMask = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 32);
APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 5);
- if ((SimplifyDemandedBits(N->getOperand(0), LHSMask, DCI)) ||
- (SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI)))
- return SDValue();
+ if (SimplifyDemandedBits(N->getOperand(0), LHSMask, DCI) ||
+ SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI)) {
+ if (N->getOpcode() != ISD::DELETED_NODE)
+ DCI.AddToWorklist(N);
+ return SDValue(N, 0);
+ }
break;
}
case RISCVISD::FMV_X_ANYEXTW_RV64: {
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