[llvm] 541effe - [RISCV] Add test case for D90339

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-10-29T14:52:24-07:00
New Revision: 541effe08278cd726a81bb11b00ddfafcbed06fd

URL: https://github.com/llvm/llvm-project/commit/541effe08278cd726a81bb11b00ddfafcbed06fd
DIFF: https://github.com/llvm/llvm-project/commit/541effe08278cd726a81bb11b00ddfafcbed06fd.diff

LOG: [RISCV] Add test case for D90339

Added: 
    llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
new file mode 100644
index 000000000000..319270ce35d0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s
+
+; This test has multiple opportunities for SimplifyDemandedBits after type
+; legalization. There are 2 opportunities on the chain feeding the LHS of the
+; shl. And one opportunity on the shift amount. We previously weren't managing
+; the DAGCombiner worklist correctly and failed to get the RHS.
+
+define i32 @foo(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mulw a0, a0, a0
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    mul a0, a0, a0
+; CHECK-NEXT:    add a0, a0, a2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    slli a1, a1, 32
+; CHECK-NEXT:    srli a1, a1, 32
+; CHECK-NEXT:    sllw a0, a0, a1
+; CHECK-NEXT:    ret
+  %b = mul i32 %x, %x
+  %c = add i32 %b, 1
+  %d = mul i32 %c, %c
+  %e = add i32 %d, %z
+  %f = add i32 %e, 1
+  %g = shl i32 %f, %y
+  ret i32 %g
+}