[llvm] 9cee87d - [AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 29 10:32:19 PDT 2020
Author: Jay Foad
Date: 2020-10-29T17:31:59Z
New Revision: 9cee87d72a0bdf07f888f61c8988159a5fe6cd74
URL: https://github.com/llvm/llvm-project/commit/9cee87d72a0bdf07f888f61c8988159a5fe6cd74
DIFF: https://github.com/llvm/llvm-project/commit/9cee87d72a0bdf07f888f61c8988159a5fe6cd74.diff
LOG: [AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds
By setting up the AsmStrings correctly we can remove some special cases
from AMDGPUInstPrinter::printOffset.
Differential Revision: https://reviews.llvm.org/D90307
Added:
Modified:
llvm/lib/Target/AMDGPU/DSInstructions.td
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 1c1e0d7097b1..2e38619e2333 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -53,7 +53,7 @@ class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
}
class DS_Real <DS_Pseudo ds> :
- InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
+ InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # ds.AsmOperands, []>,
Enc64 {
let isPseudo = 0;
@@ -87,7 +87,7 @@ class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs),
(ins rc:$data0, offset:$offset, gds:$gds),
- "$data0$offset$gds"> {
+ " $data0$offset$gds"> {
let has_addr = 0;
let has_data1 = 0;
@@ -98,7 +98,7 @@ class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs),
(ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
- "$addr, $data0$offset$gds"> {
+ " $addr, $data0$offset$gds"> {
let has_data1 = 0;
let has_vdst = 0;
@@ -118,7 +118,7 @@ class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs),
(ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
- "$addr, $data0, $data1$offset$gds"> {
+ " $addr, $data0, $data1$offset$gds"> {
let has_vdst = 0;
}
@@ -138,7 +138,7 @@ class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
(outs),
(ins VGPR_32:$addr, rc:$data0, rc:$data1,
offset0:$offset0, offset1:$offset1, gds:$gds),
- "$addr, $data0, $data1$offset0$offset1$gds"> {
+ " $addr, $data0, $data1$offset0$offset1$gds"> {
let has_vdst = 0;
let has_offset = 0;
@@ -157,7 +157,7 @@ class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs rc:$vdst),
(ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
- "$vdst, $addr, $data0$offset$gds"> {
+ " $vdst, $addr, $data0$offset$gds"> {
let hasPostISelHook = 1;
let has_data1 = 0;
@@ -181,7 +181,7 @@ class DS_1A2D_RET<string opName,
: DS_Pseudo<opName,
(outs rc:$vdst),
(ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
- "$vdst, $addr, $data0, $data1$offset$gds"> {
+ " $vdst, $addr, $data0, $data1$offset$gds"> {
let hasPostISelHook = 1;
}
@@ -205,7 +205,7 @@ class DS_1A2D_Off8_RET<string opName,
: DS_Pseudo<opName,
(outs rc:$vdst),
(ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
- "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
+ " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
let has_offset = 0;
let AsmMatchConverter = "cvtDSOffset01";
@@ -230,7 +230,7 @@ class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0
!if(HasTiedOutput,
(ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
(ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
- "$vdst, $addr$offset$gds"> {
+ " $vdst, $addr$offset$gds"> {
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
let has_data0 = 0;
@@ -252,7 +252,7 @@ class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs rc:$vdst),
(ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
- "$vdst, $addr$offset0$offset1$gds"> {
+ " $vdst, $addr$offset0$offset1$gds"> {
let has_offset = 0;
let has_data0 = 0;
@@ -271,7 +271,7 @@ multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
(outs VGPR_32:$vdst),
(ins VGPR_32:$addr, offset:$offset),
- "$vdst, $addr$offset gds"> {
+ " $vdst, $addr$offset gds"> {
let has_data0 = 0;
let has_data1 = 0;
@@ -283,7 +283,7 @@ class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
class DS_0A_RET <string opName> : DS_Pseudo<opName,
(outs VGPR_32:$vdst),
(ins offset:$offset, gds:$gds),
- "$vdst$offset$gds"> {
+ " $vdst$offset$gds"> {
let mayLoad = 1;
let mayStore = 1;
@@ -296,7 +296,7 @@ class DS_0A_RET <string opName> : DS_Pseudo<opName,
class DS_1A <string opName> : DS_Pseudo<opName,
(outs),
(ins VGPR_32:$addr, offset:$offset, gds:$gds),
- "$addr$offset$gds"> {
+ " $addr$offset$gds"> {
let mayLoad = 1;
let mayStore = 1;
@@ -336,7 +336,7 @@ class DS_GWS_0D <string opName>
class DS_GWS_1D <string opName>
: DS_GWS<opName,
- (ins VGPR_32:$data0, offset:$offset), "$data0$offset gds"> {
+ (ins VGPR_32:$data0, offset:$offset), " $data0$offset gds"> {
let has_gws_data0 = 1;
let hasSideEffects = 1;
@@ -364,7 +364,7 @@ class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
: DS_Pseudo<opName,
(outs VGPR_32:$vdst),
(ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
- "$vdst, $addr, $data0$offset",
+ " $vdst, $addr, $data0$offset",
[(set i32:$vdst,
(node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 6abbe258bd5e..79ee34d38b87 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -136,7 +136,7 @@ void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
uint16_t Imm = MI->getOperand(OpNo).getImm();
if (Imm != 0) {
- O << ((OpNo == 0)? "offset:" : " offset:");
+ O << " offset:";
printU16ImmDecOperand(MI, OpNo, O);
}
}
@@ -146,7 +146,7 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
uint16_t Imm = MI->getOperand(OpNo).getImm();
if (Imm != 0) {
- O << ((OpNo == 0)? "offset:" : " offset:");
+ O << " offset:";
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
bool IsFlatSeg = !(Desc.TSFlags & SIInstrFlags::IsNonFlatSeg);
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
index f8520573f5ed..2ac611125998 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
@@ -3623,7 +3623,7 @@
# GFX10: ds_gws_sema_br v255 offset:65535 gds ; encoding: [0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00]
0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00
-# GFX10: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00
# GFX10: ds_gws_sema_p offset:4660 gds ; encoding: [0x34,0x12,0x72,0xd8,0x00,0x00,0x00,0x00]
@@ -3632,7 +3632,7 @@
# GFX10: ds_gws_sema_p offset:65535 gds ; encoding: [0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00]
0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00
-# GFX10: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00
# GFX10: ds_gws_sema_release_all offset:4660 gds ; encoding: [0x34,0x12,0x62,0xd8,0x00,0x00,0x00,0x00]
@@ -3641,7 +3641,7 @@
# GFX10: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00
-# GFX10: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00
# GFX10: ds_gws_sema_v offset:4660 gds ; encoding: [0x34,0x12,0x6a,0xd8,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
index 182a1c18dc2f..55543719a8ae 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
@@ -2277,7 +2277,7 @@
# CHECK: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00
-# CHECK: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00
# CHECK: ds_gws_sema_release_all offset:4 gds ; encoding: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
@@ -2298,7 +2298,7 @@
# CHECK: ds_gws_sema_v offset:65535 gds ; encoding: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00
-# CHECK: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00
# CHECK: ds_gws_sema_v offset:4 gds ; encoding: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
@@ -2319,7 +2319,7 @@
# CHECK: ds_gws_sema_p offset:65535 gds ; encoding: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00
-# CHECK: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00
# CHECK: ds_gws_sema_p offset:4 gds ; encoding: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
index 18cd52d09222..f9f9cd309330 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
@@ -2421,7 +2421,7 @@
# CHECK: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00
-# CHECK: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00
# CHECK: ds_gws_sema_release_all offset:4 gds ; encoding: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
@@ -2442,7 +2442,7 @@
# CHECK: ds_gws_sema_v offset:65535 gds ; encoding: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00
-# CHECK: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00
# CHECK: ds_gws_sema_v offset:4 gds ; encoding: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
@@ -2463,7 +2463,7 @@
# CHECK: ds_gws_sema_p offset:65535 gds ; encoding: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00
-# CHECK: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+# CHECK: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00
# CHECK: ds_gws_sema_p offset:4 gds ; encoding: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
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