[PATCH] D90404: [AMDGPU] Add alignment check for v3 to v4 load type promotion

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas created this revision.
cdevadas added reviewers: tpr, arsenm, nhaehnle.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, dstuttard, yaxunl, jvesely, kzhuravl.
Herald added a project: LLVM.
cdevadas requested review of this revision.
Herald added a subscriber: wdng.

It should be enabled only when the load alignment is at least 16-byte.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90404

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/bfi_int.ll
  llvm/test/CodeGen/AMDGPU/fshl.ll
  llvm/test/CodeGen/AMDGPU/fshr.ll
  llvm/test/CodeGen/AMDGPU/kernel-args.ll
  llvm/test/CodeGen/AMDGPU/merge-stores.ll
  llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
  llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
  llvm/test/CodeGen/AMDGPU/sign_extend.ll
  llvm/test/CodeGen/AMDGPU/store-local.96.ll
  llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll

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