[PATCH] D88496: [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz
Nicholas Guy via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 29 08:17:55 PDT 2020
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGeb9fe24eaf2d: [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz (authored by NickGuy).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D88496/new/
https://reviews.llvm.org/D88496
Files:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/test/CodeGen/Thumb2/constant-hoisting.ll
llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
Index: llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
===================================================================
--- llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
+++ llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
@@ -45,15 +45,13 @@
body: |
; CHECK-LABEL: name: branch_entry
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1, %bb.2
+ ; CHECK: successors: %bb.1
; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r0 = tLDRBi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.command_set, align 4)
; CHECK: dead renamable $r0, $cpsr = tLSLri killed renamable $r0, 24, 14 /* CC::al */, $noreg
- ; CHECK: t2Bcc %bb.2, 4 /* CC::mi */, killed $cpsr
- ; CHECK: bb.1.land.end:
- ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
- ; CHECK: bb.2.land.rhs:
+ ; CHECK: $r0, dead $noreg = tMOVi8 0, 5 /* CC::pl */, $cpsr
+ ; CHECK: tBX_RET 5 /* CC::pl */, killed $cpsr, implicit killed $r0
+ ; CHECK: bb.1.land.rhs:
; CHECK: liveins: $r1, $r2
; CHECK: $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg
; CHECK: $r1 = tMOVr killed $r2, 14 /* CC::al */, $noreg
Index: llvm/test/CodeGen/Thumb2/constant-hoisting.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/constant-hoisting.ll
+++ llvm/test/CodeGen/Thumb2/constant-hoisting.ll
@@ -39,9 +39,17 @@
; CHECK-V7M-NEXT: cmp r2, #50
; CHECK-V7M-NEXT: beq .LBB0_5
; CHECK-V7M-NEXT: cmp r2, #1
-; CHECK-V7M-NEXT: beq .LBB0_7
+; CHECK-V7M-NEXT: ittt eq
+; CHECK-V7M-NEXT: addeq r0, r1
+; CHECK-V7M-NEXT: addeq r0, #1
+; CHECK-V7M-NEXT: bxeq lr
+; CHECK-V7M-NEXT: .LBB0_2:
; CHECK-V7M-NEXT: cmp r2, #30
-; CHECK-V7M-NEXT: beq .LBB0_8
+; CHECK-V7M-NEXT: ittt eq
+; CHECK-V7M-NEXT: addeq r0, r1
+; CHECK-V7M-NEXT: addeq r0, #2
+; CHECK-V7M-NEXT: bxeq lr
+; CHECK-V7M-NEXT: .LBB0_3:
; CHECK-V7M-NEXT: cbnz r2, .LBB0_6
; CHECK-V7M-NEXT: add r0, r1
; CHECK-V7M-NEXT: bx lr
@@ -50,14 +58,6 @@
; CHECK-V7M-NEXT: adds r0, #4
; CHECK-V7M-NEXT: .LBB0_6:
; CHECK-V7M-NEXT: bx lr
-; CHECK-V7M-NEXT: .LBB0_7:
-; CHECK-V7M-NEXT: add r0, r1
-; CHECK-V7M-NEXT: adds r0, #1
-; CHECK-V7M-NEXT: bx lr
-; CHECK-V7M-NEXT: .LBB0_8:
-; CHECK-V7M-NEXT: add r0, r1
-; CHECK-V7M-NEXT: adds r0, #2
-; CHECK-V7M-NEXT: bx lr
; CHECK-V7M-NEXT: .p2align 2
; CHECK-V7M-NEXT: .LCPI0_0:
; CHECK-V7M-NEXT: .long 537923600
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -603,8 +603,17 @@
bool Found = false;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
- if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
- (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
+ bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR);
+ bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR;
+ if (ClobbersCPSR || IsCPSR) {
+
+ // Filter out T1 instructions that have a dead CPSR,
+ // allowing IT blocks to be generated containing T1 instructions
+ const MCInstrDesc &MCID = MI.getDesc();
+ if (MCID.TSFlags & ARMII::ThumbArithFlagSetting && MO.isDead() &&
+ SkipDead)
+ continue;
+
Pred.push_back(MO);
Found = true;
}
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