[llvm] eb9fe24 - [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz

[Nicholas Guy via llvm-commits]

Author: Nicholas Guy
Date: 2020-10-29T15:17:31Z
New Revision: eb9fe24eaf2d602a5b5b59d253ad4946d850bd54

URL: https://github.com/llvm/llvm-project/commit/eb9fe24eaf2d602a5b5b59d253ad4946d850bd54
DIFF: https://github.com/llvm/llvm-project/commit/eb9fe24eaf2d602a5b5b59d253ad4946d850bd54.diff

LOG: [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz

Fixes a regression caused by D82439, in which IT blocks were no longer being generated when -Oz is present.

Differential Revision: https://reviews.llvm.org/D88496

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/test/CodeGen/Thumb2/constant-hoisting.ll
    llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 942da9769195..c0d5ae4dec27 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -603,8 +603,17 @@ bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI,
   bool Found = false;
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI.getOperand(i);
-    if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
-        (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
+    bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR);
+    bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR;
+    if (ClobbersCPSR || IsCPSR) {
+
+      // Filter out T1 instructions that have a dead CPSR,
+      // allowing IT blocks to be generated containing T1 instructions
+      const MCInstrDesc &MCID = MI.getDesc();
+      if (MCID.TSFlags & ARMII::ThumbArithFlagSetting && MO.isDead() &&
+          SkipDead)
+        continue;
+
       Pred.push_back(MO);
       Found = true;
     }

diff  --git a/llvm/test/CodeGen/Thumb2/constant-hoisting.ll b/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
index 161259fa5e23..5a2c01031d3c 100644
--- a/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
+++ b/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
@@ -39,9 +39,17 @@ define i32 @test_values(i32 %a, i32 %b) minsize optsize {
 ; CHECK-V7M-NEXT:    cmp r2, #50
 ; CHECK-V7M-NEXT:    beq .LBB0_5
 ; CHECK-V7M-NEXT:    cmp r2, #1
-; CHECK-V7M-NEXT:    beq .LBB0_7
+; CHECK-V7M-NEXT:    ittt eq
+; CHECK-V7M-NEXT:    addeq r0, r1
+; CHECK-V7M-NEXT:    addeq r0, #1
+; CHECK-V7M-NEXT:    bxeq lr
+; CHECK-V7M-NEXT:  .LBB0_2:
 ; CHECK-V7M-NEXT:    cmp r2, #30
-; CHECK-V7M-NEXT:    beq .LBB0_8
+; CHECK-V7M-NEXT:    ittt eq
+; CHECK-V7M-NEXT:    addeq r0, r1
+; CHECK-V7M-NEXT:    addeq r0, #2
+; CHECK-V7M-NEXT:    bxeq lr
+; CHECK-V7M-NEXT:  .LBB0_3:
 ; CHECK-V7M-NEXT:    cbnz r2, .LBB0_6
 ; CHECK-V7M-NEXT:    add r0, r1
 ; CHECK-V7M-NEXT:    bx lr
@@ -50,14 +58,6 @@ define i32 @test_values(i32 %a, i32 %b) minsize optsize {
 ; CHECK-V7M-NEXT:    adds r0, #4
 ; CHECK-V7M-NEXT:  .LBB0_6:
 ; CHECK-V7M-NEXT:    bx lr
-; CHECK-V7M-NEXT:  .LBB0_7:
-; CHECK-V7M-NEXT:    add r0, r1
-; CHECK-V7M-NEXT:    adds r0, #1
-; CHECK-V7M-NEXT:    bx lr
-; CHECK-V7M-NEXT:  .LBB0_8:
-; CHECK-V7M-NEXT:    add r0, r1
-; CHECK-V7M-NEXT:    adds r0, #2
-; CHECK-V7M-NEXT:    bx lr
 ; CHECK-V7M-NEXT:    .p2align 2
 ; CHECK-V7M-NEXT:  .LCPI0_0:
 ; CHECK-V7M-NEXT:    .long 537923600

diff  --git a/llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir b/llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
index 0138f0a509fe..c03d8682b924 100644
--- a/llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
+++ b/llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
@@ -45,15 +45,13 @@ machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: branch_entry
   ; CHECK: bb.0.entry:
-  ; CHECK:   successors: %bb.1, %bb.2
+  ; CHECK:   successors: %bb.1
   ; CHECK:   liveins: $r0, $r1, $r2
   ; CHECK:   renamable $r0 = tLDRBi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.command_set, align 4)
   ; CHECK:   dead renamable $r0, $cpsr = tLSLri killed renamable $r0, 24, 14 /* CC::al */, $noreg
-  ; CHECK:   t2Bcc %bb.2, 4 /* CC::mi */, killed $cpsr
-  ; CHECK: bb.1.land.end:
-  ; CHECK:   $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
-  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
-  ; CHECK: bb.2.land.rhs:
+  ; CHECK:   $r0, dead $noreg = tMOVi8 0, 5 /* CC::pl */, $cpsr
+  ; CHECK:   tBX_RET 5 /* CC::pl */, killed $cpsr, implicit killed $r0
+  ; CHECK: bb.1.land.rhs:
   ; CHECK:   liveins: $r1, $r2
   ; CHECK:   $r0 = tMOVr killed $r1, 14 /* CC::al */, $noreg
   ; CHECK:   $r1 = tMOVr killed $r2, 14 /* CC::al */, $noreg