[llvm] a442fad - [AMDGPU] Fix double space in disassembly of s_set_gpr_idx_mode

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2020-10-29T14:54:33Z
New Revision: a442fad911b3da4ba39a14539c5a100b5935341e

URL: https://github.com/llvm/llvm-project/commit/a442fad911b3da4ba39a14539c5a100b5935341e
DIFF: https://github.com/llvm/llvm-project/commit/a442fad911b3da4ba39a14539c5a100b5935341e.diff

LOG: [AMDGPU] Fix double space in disassembly of s_set_gpr_idx_mode

Differential Revision: https://reviews.llvm.org/D90374

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
    llvm/lib/Target/AMDGPU/SOPInstructions.td
    llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
    llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 8a5f4b58b6fd..6abbe258bd5e 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1168,9 +1168,9 @@ void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
   unsigned Val = MI->getOperand(OpNo).getImm();
 
   if ((Val & ~ENABLE_MASK) != 0) {
-    O << " " << formatHex(static_cast<uint64_t>(Val));
+    O << formatHex(static_cast<uint64_t>(Val));
   } else {
-    O << " gpr_idx(";
+    O << "gpr_idx(";
     bool NeedComma = false;
     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
       if (Val & (1 << ModeId)) {

diff  --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 77c7e6068258..08966d7d62eb 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1036,7 +1036,7 @@ def S_SET_GPR_IDX_ON : SOPC_Pseudo <
   "s_set_gpr_idx_on" ,
   (outs),
   (ins SSrc_b32:$src0, GPRIdxMode:$src1),
-  "$src0,$src1"> {
+  "$src0, $src1"> {
   let Defs = [M0, MODE]; // No scc def
   let Uses = [M0, MODE]; // Other bits of mode, m0 unmodified.
   let hasSideEffects = 1; // Sets mode.gpr_idx_en
@@ -1289,7 +1289,6 @@ def S_SET_GPR_IDX_OFF : SOPP_Pseudo<"s_set_gpr_idx_off", (ins) > {
 let SubtargetPredicate = HasVGPRIndexMode in {
 def S_SET_GPR_IDX_MODE : SOPP_Pseudo<"s_set_gpr_idx_mode", (ins GPRIdxMode:$simm16),
   "$simm16"> {
-  /*"s_set_gpr_idx_mode$simm16"> {*/
   let Defs = [M0, MODE];
   let Uses = [MODE];
 }

diff  --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
index 70f8e6651516..182a1c18dc2f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
@@ -23703,13 +23703,13 @@
 # CHECK: s_set_gpr_idx_off                       ; encoding: [0x00,0x00,0x9c,0xbf]
 0x00,0x00,0x9c,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx()           ; encoding: [0x00,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx()            ; encoding: [0x00,0x00,0x9d,0xbf]
 0x00,0x00,0x9d,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx(SRC0)       ; encoding: [0x01,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0)        ; encoding: [0x01,0x00,0x9d,0xbf]
 0x01,0x00,0x9d,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
 0x0f,0x00,0x9d,0xbf
 
 # CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x     ; encoding: [0x01,0x00,0x14,0xd4]

diff  --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
index 62fae4a5b775..18cd52d09222 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
@@ -20577,13 +20577,13 @@
 # CHECK: s_set_gpr_idx_off                       ; encoding: [0x00,0x00,0x9c,0xbf]
 0x00,0x00,0x9c,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx()           ; encoding: [0x00,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx()            ; encoding: [0x00,0x00,0x9d,0xbf]
 0x00,0x00,0x9d,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx(SRC0)       ; encoding: [0x01,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0)        ; encoding: [0x01,0x00,0x9d,0xbf]
 0x01,0x00,0x9d,0xbf
 
-# CHECK: s_set_gpr_idx_mode  gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
+# CHECK: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
 0x0f,0x00,0x9d,0xbf
 
 # CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x     ; encoding: [0x01,0x00,0x14,0xd4]