[PATCH] D90383: [VE] Support register aliases in llvm-mc

[Kazushi Marukawa via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG07d199660104: [VE] Support register aliases in llvm-mc (authored by kaz7).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90383/new/

https://reviews.llvm.org/D90383

Files:
  llvm/lib/Target/VE/VERegisterInfo.td
  llvm/test/MC/VE/register.s


Index: llvm/test/MC/VE/register.s
===================================================================
--- /dev/null
+++ llvm/test/MC/VE/register.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc -triple=ve %s -o - | FileCheck %s
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+### Test registers with specific names like "%sp"
+
+        subu.l %fp, %sp, %s0
+        brge.l.t %sp, %sl, 1f
+        ld %s63, 0x18(,%tp)
+1:
+        or %got, 0, %plt
+        b.l (,%lr)
+
+
+# CHECK:        subu.l %s9, %s11, %s0
+# CHECK-NEXT:   brge.l.t %s11, %s8, .Ltmp0
+# CHECK-NEXT:   ld %s63, 24(, %s14)
+# CHECK-NEXT: .Ltmp0:
+# CHECK-NEXT:   or %s15, 0, %s16
+# CHECK-NEXT:   b.l (, %s10)
+
+# CHECK-INST:        subu.l %s9, %s11, %s0
+# CHECK-INST-NEXT:   brge.l.t %s11, %s8, 16
+# CHECK-INST-NEXT:   ld %s63, 24(, %s14)
+# CHECK-INST-NEXT:   or %s15, 0, %s16
+# CHECK-INST-NEXT:   b.l (, %s10)
Index: llvm/lib/Target/VE/VERegisterInfo.td
===================================================================
--- llvm/lib/Target/VE/VERegisterInfo.td
+++ llvm/lib/Target/VE/VERegisterInfo.td
@@ -112,10 +112,21 @@
                    DwarfRegNum<[I]>;
 
 // Generic integer registers - 64 bits wide
-let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in
-foreach I = 0-63 in
-  def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)],
-                   ["s"#I]>, DwarfRegNum<[I]>;
+let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in {
+  // Several registers have specific names, so add them to one of aliases.
+  def SX8 : VEReg<8, "s8", [SW8, SF8], ["s8", "sl"]>, DwarfRegNum<[8]>;
+  def SX9 : VEReg<9, "s9", [SW9, SF9], ["s9", "fp"]>, DwarfRegNum<[9]>;
+  def SX10 : VEReg<10, "s10", [SW10, SF10], ["s10", "lr"]>, DwarfRegNum<[10]>;
+  def SX11 : VEReg<11, "s11", [SW11, SF11], ["s11", "sp"]>, DwarfRegNum<[11]>;
+  def SX14 : VEReg<14, "s14", [SW14, SF14], ["s14", "tp"]>, DwarfRegNum<[14]>;
+  def SX15 : VEReg<15, "s15", [SW15, SF15], ["s15", "got"]>, DwarfRegNum<[15]>;
+  def SX16 : VEReg<16, "s16", [SW16, SF16], ["s16", "plt"]>, DwarfRegNum<[16]>;
+
+  // Other generic registers.
+  foreach I = { 0-7, 12-13, 17-63 } in
+    def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)],
+                     ["s"#I]>, DwarfRegNum<[I]>;
+}
 
 // Aliases of the S* registers used to hold 128-bit for values (long doubles).
 // Following foreach represents something like:


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