[PATCH] D90387: [VE] Add missing BCR format

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka.
kaz7 added projects: LLVM, VE.
Herald added subscribers: llvm-commits, hiraditya.
kaz7 requested review of this revision.

Add missing "BCR %sy, 0, target" format instruction and a regression
test for this format.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90387

Files:
  llvm/lib/Target/VE/VEInstrInfo.td
  llvm/test/MC/VE/BCR.s


Index: llvm/test/MC/VE/BCR.s
===================================================================
--- llvm/test/MC/VE/BCR.s
+++ llvm/test/MC/VE/BCR.s
@@ -19,6 +19,10 @@
 # CHECK-ENCODING: encoding: [0xe0,0x00,0x00,0x00,0x94,0x17,0xc1,0x18]
 brgt.s 23, %s20, 224
 
+# CHECK-INST: brlt.l %s18, 0, -224
+# CHECK-ENCODING: encoding: [0x20,0xff,0xff,0xff,0x00,0x92,0x02,0x18]
+brlt.l %s18, 0, -224
+
 # CHECK-INST: brlt.l.t 23, %s20, -224
 # CHECK-ENCODING: encoding: [0x20,0xff,0xff,0xff,0x94,0x17,0x32,0x18]
 brlt.l.t 23, %s20, -224
@@ -31,6 +35,10 @@
 # CHECK-ENCODING: encoding: [0x20,0xff,0xff,0xff,0x94,0x17,0x44,0x18]
 breq.d 23, %s20, -224
 
+# CHECK-INST: breq.d %s20, 0, -224
+# CHECK-ENCODING: encoding: [0x20,0xff,0xff,0xff,0x00,0x94,0x44,0x18]
+breq.d %s20, 0, -224
+
 # CHECK-INST: brge.s.t 23, %s20, 8192
 # CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x94,0x17,0xf5,0x18]
 brge.s.t 23, %s20, 8192
Index: llvm/lib/Target/VE/VEInstrInfo.td
===================================================================
--- llvm/lib/Target/VE/VEInstrInfo.td
+++ llvm/lib/Target/VE/VEInstrInfo.td
@@ -205,6 +205,12 @@
   let PrintMethod = "printMImmOperand";
 }
 
+// zerofp - Generic fp immediate zero value.
+def zerofp : Operand<i32>, PatLeaf<(fpimm), [{
+    return getFpImmVal(N) == 0; }]> {
+  let ParserMatchClass = ZeroAsmOperand;
+}
+
 // simm7fp - Generic fp immediate value.
 def simm7fp : Operand<i32>, PatLeaf<(fpimm), [{
     return isInt<7>(getFpImmVal(N));
@@ -827,10 +833,17 @@
               !strconcat(opcStr, ".t ", cmpStr, "$imm32")>;
 }
 multiclass BCRm<string opcStr, string opcStrAt, string opcStrAf, bits<8> opc,
-               RegisterClass RC, Operand immOp> {
+               RegisterClass RC, Operand immOp, Operand zeroOp> {
   defm rr : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, RC:$sy, RC:$sz)>;
   let cy = 0 in
-  defm ir : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy, RC:$sz)>;
+  defm ir : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy,
+                                                    RC:$sz)>;
+  let cz = 0 in
+  defm rz : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, RC:$sy,
+                                                    zeroOp:$sz)>;
+  let cy = 0, cz = 0 in
+  defm iz : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy,
+                                                    zeroOp:$sz)>;
   let cy = 0, sy = 0, cz = 0, sz = 0, cf = 15 /* AT */, isBarrier = 1 in
   defm a : BCRbpfm<opcStrAt, "", opc, (ins)>;
   let cy = 0, sy = 0, cz = 0, sz = 0, cf = 0 /* AF */ in
@@ -1409,13 +1422,13 @@
 
 // Section 8.8.4 - BCR (Branch on Condition Relative)
 let cx = 0, cx2 = 0 in
-defm BRCFL : BCRm<"br${cf}.l", "br.l", "braf.l", 0x18, I64, simm7>;
+defm BRCFL : BCRm<"br${cf}.l", "br.l", "braf.l", 0x18, I64, simm7, zero>;
 let cx = 1, cx2 = 0 in
-defm BRCFW : BCRm<"br${cf}.w", "br.w", "braf.w", 0x18, I32, simm7>;
+defm BRCFW : BCRm<"br${cf}.w", "br.w", "braf.w", 0x18, I32, simm7, zero>;
 let cx = 0, cx2 = 1 in
-defm BRCFD : BCRm<"br${cf}.d", "br.d", "braf.d", 0x18, I64, simm7fp>;
+defm BRCFD : BCRm<"br${cf}.d", "br.d", "braf.d", 0x18, I64, simm7fp, zerofp>;
 let cx = 1, cx2 = 1 in
-defm BRCFS : BCRm<"br${cf}.s", "br.s", "braf.s", 0x18, F32, simm7fp>;
+defm BRCFS : BCRm<"br${cf}.s", "br.s", "braf.s", 0x18, F32, simm7fp, zerofp>;
 
 // Section 8.8.5 - BSIC (Branch and Save IC)
 let isCall = 1, hasSideEffects = 0, DecoderMethod = "DecodeCall" in


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