[PATCH] D89777: [TableGen][SchedModels] Fix read/write variant substitution

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks, A57 changes sounds OK to me.

I see code in build/lib/Target/AArch64/AArch64GenSubtargetInfo.inc that has changed like this:

    case 951: // STRDroX                                   |  25643   case 951: // STRDroX                                      
      if (SchedModel->getProcessorID() == 1) { // CycloneMo|  25644     if (SchedModel->getProcessorID() == 1) { // CycloneModel
        if (AArch64InstrInfo::isScaledAddr(*MI))           |  25645       if (AArch64InstrInfo::isScaledAddr(*MI))              
          return 1053; // (WriteIS_WriteST)_ReadBaseRS     |  25646         return 1055; // (WriteIS_WriteST)                   
        return 1054; // WriteST_ReadDefault                |  25647       return 1056; // WriteST                               
  ---------------------------------------------------------|  25648       if (AArch64InstrInfo::isScaledAddr(*MI))              
  ---------------------------------------------------------|  25649         return 1053; // _ReadBaseRS                         
  ---------------------------------------------------------|  25650       return 1054; // _ReadDefault                          
      }                                                    |  25651     }                                                       

Is that the merging reads and writes if they share the same processor model?



================
Comment at: llvm/utils/TableGen/CodeGenSchedule.cpp:1653
+  // craeted empty transition.
+  // TODO: Merge read and write transitions if they share the same
+  // processor model.
----------------
I feel like we might need to do this.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89777/new/

https://reviews.llvm.org/D89777